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Macros
Peripheral_Registers_Bits_Definition
CMSIS » Stm32f4xx » Exported_constants

Macros

#define ADC_SR_AWD   ((uint8_t)0x01)
 
#define ADC_SR_EOC   ((uint8_t)0x02)
 
#define ADC_SR_JEOC   ((uint8_t)0x04)
 
#define ADC_SR_JSTRT   ((uint8_t)0x08)
 
#define ADC_SR_STRT   ((uint8_t)0x10)
 
#define ADC_SR_OVR   ((uint8_t)0x20)
 
#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
 
#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
 
#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
 
#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
 
#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
 
#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
 
#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)
 
#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)
 
#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
 
#define ADC_CR1_SCAN   ((uint32_t)0x00000100)
 
#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
 
#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)
 
#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)
 
#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
 
#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
 
#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
 
#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
 
#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
 
#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
 
#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)
 
#define ADC_CR1_RES   ((uint32_t)0x03000000)
 
#define ADC_CR1_RES_0   ((uint32_t)0x01000000)
 
#define ADC_CR1_RES_1   ((uint32_t)0x02000000)
 
#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)
 
#define ADC_CR2_ADON   ((uint32_t)0x00000001)
 
#define ADC_CR2_CONT   ((uint32_t)0x00000002)
 
#define ADC_CR2_DMA   ((uint32_t)0x00000100)
 
#define ADC_CR2_DDS   ((uint32_t)0x00000200)
 
#define ADC_CR2_EOCS   ((uint32_t)0x00000400)
 
#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)
 
#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)
 
#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)
 
#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)
 
#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)
 
#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)
 
#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)
 
#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)
 
#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)
 
#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)
 
#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)
 
#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)
 
#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)
 
#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)
 
#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)
 
#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)
 
#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)
 
#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)
 
#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)
 
#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)
 
#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)
 
#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)
 
#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)
 
#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)
 
#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)
 
#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)
 
#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)
 
#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)
 
#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)
 
#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)
 
#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)
 
#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)
 
#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)
 
#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)
 
#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)
 
#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)
 
#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)
 
#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)
 
#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)
 
#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)
 
#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)
 
#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)
 
#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)
 
#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)
 
#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)
 
#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)
 
#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)
 
#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)
 
#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)
 
#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)
 
#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)
 
#define ADC_SMPR1_SMP18   ((uint32_t)0x07000000)
 
#define ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)
 
#define ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)
 
#define ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)
 
#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)
 
#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)
 
#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)
 
#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)
 
#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)
 
#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)
 
#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)
 
#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)
 
#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)
 
#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)
 
#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)
 
#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)
 
#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)
 
#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)
 
#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)
 
#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)
 
#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)
 
#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)
 
#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)
 
#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)
 
#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)
 
#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)
 
#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)
 
#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)
 
#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)
 
#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)
 
#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)
 
#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)
 
#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)
 
#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)
 
#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)
 
#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)
 
#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)
 
#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)
 
#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)
 
#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)
 
#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)
 
#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)
 
#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)
 
#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)
 
#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)
 
#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)
 
#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)
 
#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)
 
#define ADC_HTR_HT   ((uint16_t)0x0FFF)
 
#define ADC_LTR_LT   ((uint16_t)0x0FFF)
 
#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)
 
#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)
 
#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)
 
#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)
 
#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)
 
#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)
 
#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)
 
#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)
 
#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)
 
#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)
 
#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)
 
#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)
 
#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)
 
#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)
 
#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)
 
#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)
 
#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)
 
#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)
 
#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)
 
#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)
 
#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)
 
#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)
 
#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)
 
#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)
 
#define ADC_SQR1_L   ((uint32_t)0x00F00000)
 
#define ADC_SQR1_L_0   ((uint32_t)0x00100000)
 
#define ADC_SQR1_L_1   ((uint32_t)0x00200000)
 
#define ADC_SQR1_L_2   ((uint32_t)0x00400000)
 
#define ADC_SQR1_L_3   ((uint32_t)0x00800000)
 
#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)
 
#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)
 
#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)
 
#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)
 
#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)
 
#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)
 
#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)
 
#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)
 
#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)
 
#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)
 
#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)
 
#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)
 
#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)
 
#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)
 
#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)
 
#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)
 
#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)
 
#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)
 
#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)
 
#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)
 
#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)
 
#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)
 
#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)
 
#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)
 
#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)
 
#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)
 
#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)
 
#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)
 
#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)
 
#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)
 
#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)
 
#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)
 
#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)
 
#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)
 
#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)
 
#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)
 
#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)
 
#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)
 
#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)
 
#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)
 
#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)
 
#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)
 
#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)
 
#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)
 
#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)
 
#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)
 
#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)
 
#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)
 
#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)
 
#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)
 
#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)
 
#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)
 
#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)
 
#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)
 
#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)
 
#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)
 
#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)
 
#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)
 
#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)
 
#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)
 
#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)
 
#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)
 
#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)
 
#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)
 
#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)
 
#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)
 
#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)
 
#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)
 
#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)
 
#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)
 
#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)
 
#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)
 
#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
 
#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
 
#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
 
#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
 
#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
 
#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
 
#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
 
#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
 
#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
 
#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
 
#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
 
#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
 
#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
 
#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
 
#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
 
#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
 
#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
 
#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
 
#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
 
#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
 
#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
 
#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
 
#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
 
#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
 
#define ADC_JSQR_JL   ((uint32_t)0x00300000)
 
#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)
 
#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)
 
#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)
 
#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)
 
#define ADC_CSR_AWD1   ((uint32_t)0x00000001)
 
#define ADC_CSR_EOC1   ((uint32_t)0x00000002)
 
#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)
 
#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)
 
#define ADC_CSR_STRT1   ((uint32_t)0x00000010)
 
#define ADC_CSR_DOVR1   ((uint32_t)0x00000020)
 
#define ADC_CSR_AWD2   ((uint32_t)0x00000100)
 
#define ADC_CSR_EOC2   ((uint32_t)0x00000200)
 
#define ADC_CSR_JEOC2   ((uint32_t)0x00000400)
 
#define ADC_CSR_JSTRT2   ((uint32_t)0x00000800)
 
#define ADC_CSR_STRT2   ((uint32_t)0x00001000)
 
#define ADC_CSR_DOVR2   ((uint32_t)0x00002000)
 
#define ADC_CSR_AWD3   ((uint32_t)0x00010000)
 
#define ADC_CSR_EOC3   ((uint32_t)0x00020000)
 
#define ADC_CSR_JEOC3   ((uint32_t)0x00040000)
 
#define ADC_CSR_JSTRT3   ((uint32_t)0x00080000)
 
#define ADC_CSR_STRT3   ((uint32_t)0x00100000)
 
#define ADC_CSR_DOVR3   ((uint32_t)0x00200000)
 
#define ADC_CCR_MULTI   ((uint32_t)0x0000001F)
 
#define ADC_CCR_MULTI_0   ((uint32_t)0x00000001)
 
#define ADC_CCR_MULTI_1   ((uint32_t)0x00000002)
 
#define ADC_CCR_MULTI_2   ((uint32_t)0x00000004)
 
#define ADC_CCR_MULTI_3   ((uint32_t)0x00000008)
 
#define ADC_CCR_MULTI_4   ((uint32_t)0x00000010)
 
#define ADC_CCR_DELAY   ((uint32_t)0x00000F00)
 
#define ADC_CCR_DELAY_0   ((uint32_t)0x00000100)
 
#define ADC_CCR_DELAY_1   ((uint32_t)0x00000200)
 
#define ADC_CCR_DELAY_2   ((uint32_t)0x00000400)
 
#define ADC_CCR_DELAY_3   ((uint32_t)0x00000800)
 
#define ADC_CCR_DDS   ((uint32_t)0x00002000)
 
#define ADC_CCR_DMA   ((uint32_t)0x0000C000)
 
#define ADC_CCR_DMA_0   ((uint32_t)0x00004000)
 
#define ADC_CCR_DMA_1   ((uint32_t)0x00008000)
 
#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)
 
#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)
 
#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)
 
#define ADC_CCR_VBATE   ((uint32_t)0x00400000)
 
#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)
 
#define ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)
 
#define ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)
 
#define CAN_MCR_INRQ   ((uint16_t)0x0001)
 
#define CAN_MCR_SLEEP   ((uint16_t)0x0002)
 
#define CAN_MCR_TXFP   ((uint16_t)0x0004)
 
#define CAN_MCR_RFLM   ((uint16_t)0x0008)
 
#define CAN_MCR_NART   ((uint16_t)0x0010)
 
#define CAN_MCR_AWUM   ((uint16_t)0x0020)
 
#define CAN_MCR_ABOM   ((uint16_t)0x0040)
 
#define CAN_MCR_TTCM   ((uint16_t)0x0080)
 
#define CAN_MCR_RESET   ((uint16_t)0x8000)
 
#define CAN_MSR_INAK   ((uint16_t)0x0001)
 
#define CAN_MSR_SLAK   ((uint16_t)0x0002)
 
#define CAN_MSR_ERRI   ((uint16_t)0x0004)
 
#define CAN_MSR_WKUI   ((uint16_t)0x0008)
 
#define CAN_MSR_SLAKI   ((uint16_t)0x0010)
 
#define CAN_MSR_TXM   ((uint16_t)0x0100)
 
#define CAN_MSR_RXM   ((uint16_t)0x0200)
 
#define CAN_MSR_SAMP   ((uint16_t)0x0400)
 
#define CAN_MSR_RX   ((uint16_t)0x0800)
 
#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)
 
#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)
 
#define CAN_TSR_ALST0   ((uint32_t)0x00000004)
 
#define CAN_TSR_TERR0   ((uint32_t)0x00000008)
 
#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)
 
#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)
 
#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)
 
#define CAN_TSR_ALST1   ((uint32_t)0x00000400)
 
#define CAN_TSR_TERR1   ((uint32_t)0x00000800)
 
#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)
 
#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)
 
#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)
 
#define CAN_TSR_ALST2   ((uint32_t)0x00040000)
 
#define CAN_TSR_TERR2   ((uint32_t)0x00080000)
 
#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)
 
#define CAN_TSR_CODE   ((uint32_t)0x03000000)
 
#define CAN_TSR_TME   ((uint32_t)0x1C000000)
 
#define CAN_TSR_TME0   ((uint32_t)0x04000000)
 
#define CAN_TSR_TME1   ((uint32_t)0x08000000)
 
#define CAN_TSR_TME2   ((uint32_t)0x10000000)
 
#define CAN_TSR_LOW   ((uint32_t)0xE0000000)
 
#define CAN_TSR_LOW0   ((uint32_t)0x20000000)
 
#define CAN_TSR_LOW1   ((uint32_t)0x40000000)
 
#define CAN_TSR_LOW2   ((uint32_t)0x80000000)
 
#define CAN_RF0R_FMP0   ((uint8_t)0x03)
 
#define CAN_RF0R_FULL0   ((uint8_t)0x08)
 
#define CAN_RF0R_FOVR0   ((uint8_t)0x10)
 
#define CAN_RF0R_RFOM0   ((uint8_t)0x20)
 
#define CAN_RF1R_FMP1   ((uint8_t)0x03)
 
#define CAN_RF1R_FULL1   ((uint8_t)0x08)
 
#define CAN_RF1R_FOVR1   ((uint8_t)0x10)
 
#define CAN_RF1R_RFOM1   ((uint8_t)0x20)
 
#define CAN_IER_TMEIE   ((uint32_t)0x00000001)
 
#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)
 
#define CAN_IER_FFIE0   ((uint32_t)0x00000004)
 
#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)
 
#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)
 
#define CAN_IER_FFIE1   ((uint32_t)0x00000020)
 
#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)
 
#define CAN_IER_EWGIE   ((uint32_t)0x00000100)
 
#define CAN_IER_EPVIE   ((uint32_t)0x00000200)
 
#define CAN_IER_BOFIE   ((uint32_t)0x00000400)
 
#define CAN_IER_LECIE   ((uint32_t)0x00000800)
 
#define CAN_IER_ERRIE   ((uint32_t)0x00008000)
 
#define CAN_IER_WKUIE   ((uint32_t)0x00010000)
 
#define CAN_IER_SLKIE   ((uint32_t)0x00020000)
 
#define CAN_ESR_EWGF   ((uint32_t)0x00000001)
 
#define CAN_ESR_EPVF   ((uint32_t)0x00000002)
 
#define CAN_ESR_BOFF   ((uint32_t)0x00000004)
 
#define CAN_ESR_LEC   ((uint32_t)0x00000070)
 
#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)
 
#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)
 
#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)
 
#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)
 
#define CAN_ESR_REC   ((uint32_t)0xFF000000)
 
#define CAN_BTR_BRP   ((uint32_t)0x000003FF)
 
#define CAN_BTR_TS1   ((uint32_t)0x000F0000)
 
#define CAN_BTR_TS2   ((uint32_t)0x00700000)
 
#define CAN_BTR_SJW   ((uint32_t)0x03000000)
 
#define CAN_BTR_LBKM   ((uint32_t)0x40000000)
 
#define CAN_BTR_SILM   ((uint32_t)0x80000000)
 
#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI0R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI0R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI1R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI1R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI2R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI2R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_RI0R_RTR   ((uint32_t)0x00000002)
 
#define CAN_RI0R_IDE   ((uint32_t)0x00000004)
 
#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)
 
#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_RI1R_RTR   ((uint32_t)0x00000002)
 
#define CAN_RI1R_IDE   ((uint32_t)0x00000004)
 
#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)
 
#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_FMR_FINIT   ((uint8_t)0x01)
 
#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)
 
#define CAN_FM1R_FBM0   ((uint16_t)0x0001)
 
#define CAN_FM1R_FBM1   ((uint16_t)0x0002)
 
#define CAN_FM1R_FBM2   ((uint16_t)0x0004)
 
#define CAN_FM1R_FBM3   ((uint16_t)0x0008)
 
#define CAN_FM1R_FBM4   ((uint16_t)0x0010)
 
#define CAN_FM1R_FBM5   ((uint16_t)0x0020)
 
#define CAN_FM1R_FBM6   ((uint16_t)0x0040)
 
#define CAN_FM1R_FBM7   ((uint16_t)0x0080)
 
#define CAN_FM1R_FBM8   ((uint16_t)0x0100)
 
#define CAN_FM1R_FBM9   ((uint16_t)0x0200)
 
#define CAN_FM1R_FBM10   ((uint16_t)0x0400)
 
#define CAN_FM1R_FBM11   ((uint16_t)0x0800)
 
#define CAN_FM1R_FBM12   ((uint16_t)0x1000)
 
#define CAN_FM1R_FBM13   ((uint16_t)0x2000)
 
#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)
 
#define CAN_FS1R_FSC0   ((uint16_t)0x0001)
 
#define CAN_FS1R_FSC1   ((uint16_t)0x0002)
 
#define CAN_FS1R_FSC2   ((uint16_t)0x0004)
 
#define CAN_FS1R_FSC3   ((uint16_t)0x0008)
 
#define CAN_FS1R_FSC4   ((uint16_t)0x0010)
 
#define CAN_FS1R_FSC5   ((uint16_t)0x0020)
 
#define CAN_FS1R_FSC6   ((uint16_t)0x0040)
 
#define CAN_FS1R_FSC7   ((uint16_t)0x0080)
 
#define CAN_FS1R_FSC8   ((uint16_t)0x0100)
 
#define CAN_FS1R_FSC9   ((uint16_t)0x0200)
 
#define CAN_FS1R_FSC10   ((uint16_t)0x0400)
 
#define CAN_FS1R_FSC11   ((uint16_t)0x0800)
 
#define CAN_FS1R_FSC12   ((uint16_t)0x1000)
 
#define CAN_FS1R_FSC13   ((uint16_t)0x2000)
 
#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)
 
#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)
 
#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)
 
#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)
 
#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)
 
#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)
 
#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)
 
#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)
 
#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)
 
#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)
 
#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)
 
#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)
 
#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)
 
#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)
 
#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)
 
#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)
 
#define CAN_FA1R_FACT0   ((uint16_t)0x0001)
 
#define CAN_FA1R_FACT1   ((uint16_t)0x0002)
 
#define CAN_FA1R_FACT2   ((uint16_t)0x0004)
 
#define CAN_FA1R_FACT3   ((uint16_t)0x0008)
 
#define CAN_FA1R_FACT4   ((uint16_t)0x0010)
 
#define CAN_FA1R_FACT5   ((uint16_t)0x0020)
 
#define CAN_FA1R_FACT6   ((uint16_t)0x0040)
 
#define CAN_FA1R_FACT7   ((uint16_t)0x0080)
 
#define CAN_FA1R_FACT8   ((uint16_t)0x0100)
 
#define CAN_FA1R_FACT9   ((uint16_t)0x0200)
 
#define CAN_FA1R_FACT10   ((uint16_t)0x0400)
 
#define CAN_FA1R_FACT11   ((uint16_t)0x0800)
 
#define CAN_FA1R_FACT12   ((uint16_t)0x1000)
 
#define CAN_FA1R_FACT13   ((uint16_t)0x2000)
 
#define CAN_F0R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F0R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F0R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F0R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F0R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F0R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F0R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F0R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F0R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F0R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F0R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F0R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F0R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F0R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F0R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F0R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F0R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F0R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F0R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F0R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F0R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F0R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F0R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F0R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F0R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F0R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F0R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F0R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F0R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F0R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F0R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F0R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F1R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F1R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F1R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F1R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F1R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F1R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F1R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F1R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F1R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F1R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F1R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F1R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F1R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F1R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F1R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F1R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F1R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F1R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F1R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F1R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F1R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F1R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F1R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F1R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F1R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F1R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F1R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F1R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F1R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F1R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F1R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F1R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F2R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F2R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F2R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F2R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F2R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F2R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F2R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F2R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F2R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F2R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F2R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F2R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F2R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F2R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F2R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F2R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F2R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F2R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F2R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F2R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F2R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F2R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F2R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F2R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F2R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F2R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F2R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F2R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F2R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F2R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F2R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F2R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F3R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F3R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F3R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F3R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F3R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F3R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F3R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F3R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F3R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F3R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F3R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F3R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F3R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F3R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F3R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F3R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F3R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F3R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F3R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F3R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F3R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F3R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F3R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F3R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F3R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F3R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F3R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F3R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F3R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F3R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F3R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F3R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F4R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F4R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F4R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F4R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F4R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F4R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F4R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F4R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F4R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F4R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F4R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F4R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F4R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F4R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F4R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F4R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F4R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F4R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F4R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F4R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F4R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F4R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F4R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F4R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F4R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F4R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F4R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F4R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F4R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F4R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F4R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F4R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F5R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F5R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F5R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F5R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F5R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F5R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F5R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F5R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F5R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F5R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F5R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F5R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F5R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F5R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F5R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F5R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F5R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F5R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F5R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F5R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F5R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F5R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F5R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F5R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F5R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F5R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F5R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F5R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F5R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F5R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F5R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F5R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F6R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F6R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F6R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F6R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F6R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F6R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F6R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F6R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F6R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F6R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F6R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F6R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F6R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F6R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F6R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F6R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F6R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F6R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F6R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F6R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F6R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F6R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F6R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F6R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F6R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F6R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F6R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F6R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F6R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F6R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F6R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F6R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F7R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F7R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F7R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F7R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F7R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F7R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F7R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F7R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F7R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F7R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F7R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F7R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F7R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F7R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F7R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F7R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F7R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F7R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F7R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F7R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F7R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F7R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F7R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F7R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F7R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F7R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F7R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F7R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F7R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F7R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F7R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F7R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F8R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F8R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F8R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F8R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F8R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F8R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F8R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F8R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F8R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F8R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F8R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F8R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F8R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F8R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F8R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F8R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F8R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F8R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F8R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F8R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F8R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F8R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F8R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F8R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F8R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F8R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F8R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F8R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F8R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F8R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F8R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F8R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F9R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F9R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F9R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F9R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F9R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F9R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F9R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F9R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F9R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F9R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F9R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F9R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F9R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F9R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F9R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F9R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F9R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F9R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F9R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F9R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F9R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F9R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F9R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F9R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F9R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F9R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F9R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F9R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F9R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F9R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F9R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F9R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F10R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F10R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F10R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F10R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F10R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F10R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F10R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F10R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F10R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F10R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F10R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F10R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F10R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F10R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F10R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F10R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F10R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F10R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F10R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F10R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F10R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F10R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F10R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F10R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F10R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F10R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F10R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F10R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F10R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F10R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F10R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F10R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F11R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F11R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F11R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F11R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F11R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F11R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F11R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F11R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F11R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F11R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F11R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F11R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F11R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F11R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F11R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F11R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F11R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F11R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F11R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F11R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F11R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F11R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F11R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F11R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F11R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F11R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F11R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F11R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F11R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F11R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F11R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F11R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F12R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F12R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F12R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F12R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F12R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F12R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F12R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F12R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F12R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F12R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F12R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F12R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F12R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F12R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F12R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F12R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F12R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F12R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F12R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F12R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F12R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F12R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F12R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F12R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F12R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F12R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F12R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F12R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F12R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F12R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F12R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F12R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F13R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F13R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F13R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F13R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F13R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F13R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F13R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F13R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F13R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F13R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F13R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F13R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F13R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F13R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F13R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F13R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F13R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F13R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F13R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F13R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F13R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F13R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F13R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F13R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F13R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F13R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F13R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F13R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F13R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F13R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F13R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F13R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F0R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F0R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F0R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F0R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F0R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F0R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F0R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F0R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F0R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F0R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F0R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F0R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F0R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F0R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F0R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F0R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F0R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F0R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F0R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F0R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F0R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F0R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F0R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F0R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F0R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F0R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F0R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F0R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F0R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F0R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F0R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F0R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F1R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F1R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F1R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F1R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F1R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F1R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F1R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F1R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F1R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F1R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F1R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F1R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F1R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F1R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F1R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F1R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F1R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F1R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F1R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F1R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F1R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F1R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F1R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F1R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F1R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F1R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F1R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F1R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F1R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F1R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F1R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F1R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F2R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F2R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F2R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F2R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F2R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F2R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F2R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F2R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F2R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F2R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F2R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F2R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F2R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F2R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F2R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F2R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F2R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F2R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F2R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F2R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F2R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F2R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F2R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F2R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F2R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F2R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F2R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F2R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F2R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F2R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F2R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F2R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F3R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F3R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F3R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F3R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F3R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F3R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F3R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F3R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F3R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F3R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F3R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F3R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F3R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F3R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F3R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F3R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F3R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F3R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F3R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F3R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F3R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F3R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F3R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F3R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F3R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F3R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F3R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F3R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F3R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F3R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F3R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F3R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F4R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F4R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F4R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F4R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F4R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F4R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F4R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F4R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F4R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F4R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F4R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F4R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F4R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F4R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F4R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F4R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F4R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F4R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F4R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F4R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F4R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F4R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F4R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F4R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F4R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F4R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F4R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F4R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F4R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F4R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F4R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F4R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F5R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F5R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F5R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F5R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F5R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F5R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F5R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F5R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F5R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F5R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F5R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F5R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F5R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F5R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F5R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F5R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F5R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F5R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F5R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F5R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F5R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F5R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F5R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F5R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F5R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F5R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F5R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F5R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F5R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F5R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F5R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F5R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F6R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F6R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F6R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F6R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F6R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F6R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F6R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F6R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F6R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F6R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F6R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F6R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F6R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F6R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F6R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F6R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F6R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F6R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F6R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F6R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F6R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F6R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F6R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F6R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F6R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F6R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F6R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F6R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F6R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F6R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F6R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F6R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F7R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F7R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F7R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F7R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F7R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F7R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F7R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F7R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F7R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F7R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F7R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F7R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F7R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F7R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F7R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F7R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F7R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F7R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F7R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F7R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F7R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F7R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F7R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F7R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F7R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F7R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F7R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F7R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F7R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F7R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F7R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F7R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F8R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F8R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F8R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F8R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F8R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F8R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F8R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F8R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F8R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F8R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F8R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F8R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F8R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F8R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F8R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F8R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F8R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F8R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F8R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F8R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F8R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F8R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F8R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F8R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F8R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F8R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F8R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F8R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F8R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F8R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F8R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F8R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F9R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F9R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F9R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F9R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F9R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F9R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F9R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F9R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F9R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F9R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F9R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F9R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F9R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F9R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F9R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F9R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F9R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F9R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F9R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F9R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F9R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F9R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F9R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F9R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F9R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F9R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F9R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F9R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F9R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F9R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F9R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F9R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F10R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F10R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F10R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F10R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F10R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F10R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F10R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F10R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F10R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F10R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F10R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F10R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F10R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F10R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F10R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F10R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F10R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F10R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F10R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F10R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F10R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F10R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F10R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F10R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F10R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F10R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F10R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F10R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F10R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F10R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F10R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F10R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F11R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F11R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F11R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F11R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F11R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F11R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F11R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F11R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F11R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F11R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F11R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F11R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F11R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F11R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F11R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F11R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F11R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F11R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F11R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F11R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F11R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F11R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F11R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F11R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F11R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F11R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F11R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F11R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F11R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F11R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F11R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F11R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F12R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F12R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F12R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F12R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F12R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F12R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F12R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F12R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F12R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F12R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F12R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F12R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F12R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F12R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F12R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F12R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F12R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F12R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F12R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F12R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F12R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F12R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F12R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F12R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F12R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F12R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F12R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F12R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F12R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F12R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F12R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F12R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F13R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F13R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F13R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F13R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F13R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F13R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F13R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F13R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F13R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F13R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F13R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F13R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F13R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F13R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F13R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F13R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F13R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F13R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F13R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F13R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F13R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F13R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F13R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F13R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F13R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F13R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F13R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F13R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F13R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F13R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F13R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F13R2_FB31   ((uint32_t)0x80000000)
 
#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
 
#define CRC_IDR_IDR   ((uint8_t)0xFF)
 
#define CRC_CR_RESET   ((uint8_t)0x01)
 
#define CRYP_CR_ALGODIR   ((uint32_t)0x00000004)
 
#define CRYP_CR_ALGOMODE   ((uint32_t)0x00000038)
 
#define CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)
 
#define CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)
 
#define CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)
 
#define CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)
 
#define CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)
 
#define CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)
 
#define CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)
 
#define CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)
 
#define CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)
 
#define CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)
 
#define CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)
 
#define CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)
 
#define CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)
 
#define CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)
 
#define CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)
 
#define CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)
 
#define CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)
 
#define CRYP_CR_FFLUSH   ((uint32_t)0x00004000)
 
#define CRYP_CR_CRYPEN   ((uint32_t)0x00008000)
 
#define CRYP_SR_IFEM   ((uint32_t)0x00000001)
 
#define CRYP_SR_IFNF   ((uint32_t)0x00000002)
 
#define CRYP_SR_OFNE   ((uint32_t)0x00000004)
 
#define CRYP_SR_OFFU   ((uint32_t)0x00000008)
 
#define CRYP_SR_BUSY   ((uint32_t)0x00000010)
 
#define CRYP_DMACR_DIEN   ((uint32_t)0x00000001)
 
#define CRYP_DMACR_DOEN   ((uint32_t)0x00000002)
 
#define CRYP_IMSCR_INIM   ((uint32_t)0x00000001)
 
#define CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)
 
#define CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)
 
#define CRYP_RISR_INRIS   ((uint32_t)0x00000002)
 
#define CRYP_MISR_INMIS   ((uint32_t)0x00000001)
 
#define CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)
 
#define DAC_CR_EN1   ((uint32_t)0x00000001)
 
#define DAC_CR_BOFF1   ((uint32_t)0x00000002)
 
#define DAC_CR_TEN1   ((uint32_t)0x00000004)
 
#define DAC_CR_TSEL1   ((uint32_t)0x00000038)
 
#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
 
#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
 
#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
 
#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)
 
#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
 
#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
 
#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)
 
#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
 
#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
 
#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
 
#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
 
#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)
 
#define DAC_CR_EN2   ((uint32_t)0x00010000)
 
#define DAC_CR_BOFF2   ((uint32_t)0x00020000)
 
#define DAC_CR_TEN2   ((uint32_t)0x00040000)
 
#define DAC_CR_TSEL2   ((uint32_t)0x00380000)
 
#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
 
#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
 
#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
 
#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)
 
#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
 
#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
 
#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)
 
#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
 
#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
 
#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
 
#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
 
#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)
 
#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
 
#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
 
#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
 
#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
 
#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
 
#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
 
#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
 
#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
 
#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
 
#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
 
#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
 
#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
 
#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
 
#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
 
#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
 
#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
 
#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
 
#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
 
#define DCMI_CR_CAPTURE   ((uint32_t)0x00000001)
 
#define DCMI_CR_CM   ((uint32_t)0x00000002)
 
#define DCMI_CR_CROP   ((uint32_t)0x00000004)
 
#define DCMI_CR_JPEG   ((uint32_t)0x00000008)
 
#define DCMI_CR_ESS   ((uint32_t)0x00000010)
 
#define DCMI_CR_PCKPOL   ((uint32_t)0x00000020)
 
#define DCMI_CR_HSPOL   ((uint32_t)0x00000040)
 
#define DCMI_CR_VSPOL   ((uint32_t)0x00000080)
 
#define DCMI_CR_FCRC_0   ((uint32_t)0x00000100)
 
#define DCMI_CR_FCRC_1   ((uint32_t)0x00000200)
 
#define DCMI_CR_EDM_0   ((uint32_t)0x00000400)
 
#define DCMI_CR_EDM_1   ((uint32_t)0x00000800)
 
#define DCMI_CR_CRE   ((uint32_t)0x00001000)
 
#define DCMI_CR_ENABLE   ((uint32_t)0x00004000)
 
#define DCMI_SR_HSYNC   ((uint32_t)0x00000001)
 
#define DCMI_SR_VSYNC   ((uint32_t)0x00000002)
 
#define DCMI_SR_FNE   ((uint32_t)0x00000004)
 
#define DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)
 
#define DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)
 
#define DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)
 
#define DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)
 
#define DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)
 
#define DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)
 
#define DCMI_IER_OVF_IE   ((uint32_t)0x00000002)
 
#define DCMI_IER_ERR_IE   ((uint32_t)0x00000004)
 
#define DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)
 
#define DCMI_IER_LINE_IE   ((uint32_t)0x00000010)
 
#define DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)
 
#define DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)
 
#define DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)
 
#define DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)
 
#define DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)
 
#define DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)
 
#define DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)
 
#define DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)
 
#define DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)
 
#define DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)
 
#define DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)
 
#define DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)
 
#define DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)
 
#define DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)
 
#define DMA_SxCR_MBURST   ((uint32_t)0x01800000)
 
#define DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)
 
#define DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)
 
#define DMA_SxCR_PBURST   ((uint32_t)0x00600000)
 
#define DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)
 
#define DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)
 
#define DMA_SxCR_ACK   ((uint32_t)0x00100000)
 
#define DMA_SxCR_CT   ((uint32_t)0x00080000)
 
#define DMA_SxCR_DBM   ((uint32_t)0x00040000)
 
#define DMA_SxCR_PL   ((uint32_t)0x00030000)
 
#define DMA_SxCR_PL_0   ((uint32_t)0x00010000)
 
#define DMA_SxCR_PL_1   ((uint32_t)0x00020000)
 
#define DMA_SxCR_PINCOS   ((uint32_t)0x00008000)
 
#define DMA_SxCR_MSIZE   ((uint32_t)0x00006000)
 
#define DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)
 
#define DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)
 
#define DMA_SxCR_PSIZE   ((uint32_t)0x00001800)
 
#define DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)
 
#define DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)
 
#define DMA_SxCR_MINC   ((uint32_t)0x00000400)
 
#define DMA_SxCR_PINC   ((uint32_t)0x00000200)
 
#define DMA_SxCR_CIRC   ((uint32_t)0x00000100)
 
#define DMA_SxCR_DIR   ((uint32_t)0x000000C0)
 
#define DMA_SxCR_DIR_0   ((uint32_t)0x00000040)
 
#define DMA_SxCR_DIR_1   ((uint32_t)0x00000080)
 
#define DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)
 
#define DMA_SxCR_TCIE   ((uint32_t)0x00000010)
 
#define DMA_SxCR_HTIE   ((uint32_t)0x00000008)
 
#define DMA_SxCR_TEIE   ((uint32_t)0x00000004)
 
#define DMA_SxCR_DMEIE   ((uint32_t)0x00000002)
 
#define DMA_SxCR_EN   ((uint32_t)0x00000001)
 
#define DMA_SxNDT   ((uint32_t)0x0000FFFF)
 
#define DMA_SxNDT_0   ((uint32_t)0x00000001)
 
#define DMA_SxNDT_1   ((uint32_t)0x00000002)
 
#define DMA_SxNDT_2   ((uint32_t)0x00000004)
 
#define DMA_SxNDT_3   ((uint32_t)0x00000008)
 
#define DMA_SxNDT_4   ((uint32_t)0x00000010)
 
#define DMA_SxNDT_5   ((uint32_t)0x00000020)
 
#define DMA_SxNDT_6   ((uint32_t)0x00000040)
 
#define DMA_SxNDT_7   ((uint32_t)0x00000080)
 
#define DMA_SxNDT_8   ((uint32_t)0x00000100)
 
#define DMA_SxNDT_9   ((uint32_t)0x00000200)
 
#define DMA_SxNDT_10   ((uint32_t)0x00000400)
 
#define DMA_SxNDT_11   ((uint32_t)0x00000800)
 
#define DMA_SxNDT_12   ((uint32_t)0x00001000)
 
#define DMA_SxNDT_13   ((uint32_t)0x00002000)
 
#define DMA_SxNDT_14   ((uint32_t)0x00004000)
 
#define DMA_SxNDT_15   ((uint32_t)0x00008000)
 
#define DMA_SxFCR_FEIE   ((uint32_t)0x00000080)
 
#define DMA_SxFCR_FS   ((uint32_t)0x00000038)
 
#define DMA_SxFCR_FS_0   ((uint32_t)0x00000008)
 
#define DMA_SxFCR_FS_1   ((uint32_t)0x00000010)
 
#define DMA_SxFCR_FS_2   ((uint32_t)0x00000020)
 
#define DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)
 
#define DMA_SxFCR_FTH   ((uint32_t)0x00000003)
 
#define DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)
 
#define DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)
 
#define DMA_LISR_TCIF3   ((uint32_t)0x08000000)
 
#define DMA_LISR_HTIF3   ((uint32_t)0x04000000)
 
#define DMA_LISR_TEIF3   ((uint32_t)0x02000000)
 
#define DMA_LISR_DMEIF3   ((uint32_t)0x01000000)
 
#define DMA_LISR_FEIF3   ((uint32_t)0x00400000)
 
#define DMA_LISR_TCIF2   ((uint32_t)0x00200000)
 
#define DMA_LISR_HTIF2   ((uint32_t)0x00100000)
 
#define DMA_LISR_TEIF2   ((uint32_t)0x00080000)
 
#define DMA_LISR_DMEIF2   ((uint32_t)0x00040000)
 
#define DMA_LISR_FEIF2   ((uint32_t)0x00010000)
 
#define DMA_LISR_TCIF1   ((uint32_t)0x00000800)
 
#define DMA_LISR_HTIF1   ((uint32_t)0x00000400)
 
#define DMA_LISR_TEIF1   ((uint32_t)0x00000200)
 
#define DMA_LISR_DMEIF1   ((uint32_t)0x00000100)
 
#define DMA_LISR_FEIF1   ((uint32_t)0x00000040)
 
#define DMA_LISR_TCIF0   ((uint32_t)0x00000020)
 
#define DMA_LISR_HTIF0   ((uint32_t)0x00000010)
 
#define DMA_LISR_TEIF0   ((uint32_t)0x00000008)
 
#define DMA_LISR_DMEIF0   ((uint32_t)0x00000004)
 
#define DMA_LISR_FEIF0   ((uint32_t)0x00000001)
 
#define DMA_HISR_TCIF7   ((uint32_t)0x08000000)
 
#define DMA_HISR_HTIF7   ((uint32_t)0x04000000)
 
#define DMA_HISR_TEIF7   ((uint32_t)0x02000000)
 
#define DMA_HISR_DMEIF7   ((uint32_t)0x01000000)
 
#define DMA_HISR_FEIF7   ((uint32_t)0x00400000)
 
#define DMA_HISR_TCIF6   ((uint32_t)0x00200000)
 
#define DMA_HISR_HTIF6   ((uint32_t)0x00100000)
 
#define DMA_HISR_TEIF6   ((uint32_t)0x00080000)
 
#define DMA_HISR_DMEIF6   ((uint32_t)0x00040000)
 
#define DMA_HISR_FEIF6   ((uint32_t)0x00010000)
 
#define DMA_HISR_TCIF5   ((uint32_t)0x00000800)
 
#define DMA_HISR_HTIF5   ((uint32_t)0x00000400)
 
#define DMA_HISR_TEIF5   ((uint32_t)0x00000200)
 
#define DMA_HISR_DMEIF5   ((uint32_t)0x00000100)
 
#define DMA_HISR_FEIF5   ((uint32_t)0x00000040)
 
#define DMA_HISR_TCIF4   ((uint32_t)0x00000020)
 
#define DMA_HISR_HTIF4   ((uint32_t)0x00000010)
 
#define DMA_HISR_TEIF4   ((uint32_t)0x00000008)
 
#define DMA_HISR_DMEIF4   ((uint32_t)0x00000004)
 
#define DMA_HISR_FEIF4   ((uint32_t)0x00000001)
 
#define DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)
 
#define DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)
 
#define DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)
 
#define DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)
 
#define DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)
 
#define DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)
 
#define DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)
 
#define DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)
 
#define DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)
 
#define DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)
 
#define DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)
 
#define DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)
 
#define DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)
 
#define DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)
 
#define DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)
 
#define DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)
 
#define DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)
 
#define DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)
 
#define DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)
 
#define DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)
 
#define DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)
 
#define DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)
 
#define DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)
 
#define DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)
 
#define DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)
 
#define DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)
 
#define DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)
 
#define DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)
 
#define DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)
 
#define DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)
 
#define DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)
 
#define DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)
 
#define DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)
 
#define DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)
 
#define DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)
 
#define DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)
 
#define DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)
 
#define DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)
 
#define DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)
 
#define DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)
 
#define EXTI_IMR_MR0   ((uint32_t)0x00000001)
 
#define EXTI_IMR_MR1   ((uint32_t)0x00000002)
 
#define EXTI_IMR_MR2   ((uint32_t)0x00000004)
 
#define EXTI_IMR_MR3   ((uint32_t)0x00000008)
 
#define EXTI_IMR_MR4   ((uint32_t)0x00000010)
 
#define EXTI_IMR_MR5   ((uint32_t)0x00000020)
 
#define EXTI_IMR_MR6   ((uint32_t)0x00000040)
 
#define EXTI_IMR_MR7   ((uint32_t)0x00000080)
 
#define EXTI_IMR_MR8   ((uint32_t)0x00000100)
 
#define EXTI_IMR_MR9   ((uint32_t)0x00000200)
 
#define EXTI_IMR_MR10   ((uint32_t)0x00000400)
 
#define EXTI_IMR_MR11   ((uint32_t)0x00000800)
 
#define EXTI_IMR_MR12   ((uint32_t)0x00001000)
 
#define EXTI_IMR_MR13   ((uint32_t)0x00002000)
 
#define EXTI_IMR_MR14   ((uint32_t)0x00004000)
 
#define EXTI_IMR_MR15   ((uint32_t)0x00008000)
 
#define EXTI_IMR_MR16   ((uint32_t)0x00010000)
 
#define EXTI_IMR_MR17   ((uint32_t)0x00020000)
 
#define EXTI_IMR_MR18   ((uint32_t)0x00040000)
 
#define EXTI_IMR_MR19   ((uint32_t)0x00080000)
 
#define EXTI_EMR_MR0   ((uint32_t)0x00000001)
 
#define EXTI_EMR_MR1   ((uint32_t)0x00000002)
 
#define EXTI_EMR_MR2   ((uint32_t)0x00000004)
 
#define EXTI_EMR_MR3   ((uint32_t)0x00000008)
 
#define EXTI_EMR_MR4   ((uint32_t)0x00000010)
 
#define EXTI_EMR_MR5   ((uint32_t)0x00000020)
 
#define EXTI_EMR_MR6   ((uint32_t)0x00000040)
 
#define EXTI_EMR_MR7   ((uint32_t)0x00000080)
 
#define EXTI_EMR_MR8   ((uint32_t)0x00000100)
 
#define EXTI_EMR_MR9   ((uint32_t)0x00000200)
 
#define EXTI_EMR_MR10   ((uint32_t)0x00000400)
 
#define EXTI_EMR_MR11   ((uint32_t)0x00000800)
 
#define EXTI_EMR_MR12   ((uint32_t)0x00001000)
 
#define EXTI_EMR_MR13   ((uint32_t)0x00002000)
 
#define EXTI_EMR_MR14   ((uint32_t)0x00004000)
 
#define EXTI_EMR_MR15   ((uint32_t)0x00008000)
 
#define EXTI_EMR_MR16   ((uint32_t)0x00010000)
 
#define EXTI_EMR_MR17   ((uint32_t)0x00020000)
 
#define EXTI_EMR_MR18   ((uint32_t)0x00040000)
 
#define EXTI_EMR_MR19   ((uint32_t)0x00080000)
 
#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)
 
#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)
 
#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)
 
#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)
 
#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)
 
#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)
 
#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)
 
#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)
 
#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)
 
#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)
 
#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)
 
#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)
 
#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)
 
#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)
 
#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)
 
#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)
 
#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)
 
#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)
 
#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)
 
#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)
 
#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)
 
#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)
 
#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)
 
#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)
 
#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)
 
#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)
 
#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)
 
#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)
 
#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)
 
#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)
 
#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)
 
#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)
 
#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)
 
#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)
 
#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)
 
#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)
 
#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)
 
#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)
 
#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)
 
#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)
 
#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
 
#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
 
#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
 
#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
 
#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
 
#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
 
#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
 
#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
 
#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
 
#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
 
#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
 
#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
 
#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
 
#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
 
#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
 
#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
 
#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
 
#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
 
#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
 
#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
 
#define EXTI_PR_PR0   ((uint32_t)0x00000001)
 
#define EXTI_PR_PR1   ((uint32_t)0x00000002)
 
#define EXTI_PR_PR2   ((uint32_t)0x00000004)
 
#define EXTI_PR_PR3   ((uint32_t)0x00000008)
 
#define EXTI_PR_PR4   ((uint32_t)0x00000010)
 
#define EXTI_PR_PR5   ((uint32_t)0x00000020)
 
#define EXTI_PR_PR6   ((uint32_t)0x00000040)
 
#define EXTI_PR_PR7   ((uint32_t)0x00000080)
 
#define EXTI_PR_PR8   ((uint32_t)0x00000100)
 
#define EXTI_PR_PR9   ((uint32_t)0x00000200)
 
#define EXTI_PR_PR10   ((uint32_t)0x00000400)
 
#define EXTI_PR_PR11   ((uint32_t)0x00000800)
 
#define EXTI_PR_PR12   ((uint32_t)0x00001000)
 
#define EXTI_PR_PR13   ((uint32_t)0x00002000)
 
#define EXTI_PR_PR14   ((uint32_t)0x00004000)
 
#define EXTI_PR_PR15   ((uint32_t)0x00008000)
 
#define EXTI_PR_PR16   ((uint32_t)0x00010000)
 
#define EXTI_PR_PR17   ((uint32_t)0x00020000)
 
#define EXTI_PR_PR18   ((uint32_t)0x00040000)
 
#define EXTI_PR_PR19   ((uint32_t)0x00080000)
 
#define FLASH_ACR_LATENCY   ((uint32_t)0x00000007)
 
#define FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)
 
#define FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)
 
#define FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)
 
#define FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)
 
#define FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)
 
#define FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)
 
#define FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)
 
#define FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)
 
#define FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)
 
#define FLASH_ACR_ICEN   ((uint32_t)0x00000200)
 
#define FLASH_ACR_DCEN   ((uint32_t)0x00000400)
 
#define FLASH_ACR_ICRST   ((uint32_t)0x00000800)
 
#define FLASH_ACR_DCRST   ((uint32_t)0x00001000)
 
#define FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)
 
#define FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)
 
#define FLASH_SR_EOP   ((uint32_t)0x00000001)
 
#define FLASH_SR_SOP   ((uint32_t)0x00000002)
 
#define FLASH_SR_WRPERR   ((uint32_t)0x00000010)
 
#define FLASH_SR_PGAERR   ((uint32_t)0x00000020)
 
#define FLASH_SR_PGPERR   ((uint32_t)0x00000040)
 
#define FLASH_SR_PGSERR   ((uint32_t)0x00000080)
 
#define FLASH_SR_BSY   ((uint32_t)0x00010000)
 
#define FLASH_CR_PG   ((uint32_t)0x00000001)
 
#define FLASH_CR_SER   ((uint32_t)0x00000002)
 
#define FLASH_CR_MER   ((uint32_t)0x00000004)
 
#define FLASH_CR_SNB_0   ((uint32_t)0x00000008)
 
#define FLASH_CR_SNB_1   ((uint32_t)0x00000010)
 
#define FLASH_CR_SNB_2   ((uint32_t)0x00000020)
 
#define FLASH_CR_SNB_3   ((uint32_t)0x00000040)
 
#define FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)
 
#define FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)
 
#define FLASH_CR_STRT   ((uint32_t)0x00010000)
 
#define FLASH_CR_EOPIE   ((uint32_t)0x01000000)
 
#define FLASH_CR_LOCK   ((uint32_t)0x80000000)
 
#define FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)
 
#define FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)
 
#define FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)
 
#define FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)
 
#define FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)
 
#define FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)
 
#define FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)
 
#define FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)
 
#define FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)
 
#define FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)
 
#define FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)
 
#define FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)
 
#define FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)
 
#define FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)
 
#define FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)
 
#define FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)
 
#define FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)
 
#define FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)
 
#define FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)
 
#define FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)
 
#define FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)
 
#define FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)
 
#define FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)
 
#define FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)
 
#define FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)
 
#define FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)
 
#define FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)
 
#define FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)
 
#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_SR2_IRS   ((uint8_t)0x01)
 
#define FSMC_SR2_ILS   ((uint8_t)0x02)
 
#define FSMC_SR2_IFS   ((uint8_t)0x04)
 
#define FSMC_SR2_IREN   ((uint8_t)0x08)
 
#define FSMC_SR2_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR2_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR2_FEMPT   ((uint8_t)0x40)
 
#define FSMC_SR3_IRS   ((uint8_t)0x01)
 
#define FSMC_SR3_ILS   ((uint8_t)0x02)
 
#define FSMC_SR3_IFS   ((uint8_t)0x04)
 
#define FSMC_SR3_IREN   ((uint8_t)0x08)
 
#define FSMC_SR3_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR3_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR3_FEMPT   ((uint8_t)0x40)
 
#define FSMC_SR4_IRS   ((uint8_t)0x01)
 
#define FSMC_SR4_ILS   ((uint8_t)0x02)
 
#define FSMC_SR4_IFS   ((uint8_t)0x04)
 
#define FSMC_SR4_IREN   ((uint8_t)0x08)
 
#define FSMC_SR4_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR4_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR4_FEMPT   ((uint8_t)0x40)
 
#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)
 
#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)
 
#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)
 
#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)
 
#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)
 
#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)
 
#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)
 
#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)
 
#define GPIO_MODER_MODER0   ((uint32_t)0x00000003)
 
#define GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)
 
#define GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)
 
#define GPIO_MODER_MODER1   ((uint32_t)0x0000000C)
 
#define GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)
 
#define GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)
 
#define GPIO_MODER_MODER2   ((uint32_t)0x00000030)
 
#define GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)
 
#define GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)
 
#define GPIO_MODER_MODER3   ((uint32_t)0x000000C0)
 
#define GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)
 
#define GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)
 
#define GPIO_MODER_MODER4   ((uint32_t)0x00000300)
 
#define GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)
 
#define GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)
 
#define GPIO_MODER_MODER5   ((uint32_t)0x00000C00)
 
#define GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)
 
#define GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)
 
#define GPIO_MODER_MODER6   ((uint32_t)0x00003000)
 
#define GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)
 
#define GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)
 
#define GPIO_MODER_MODER7   ((uint32_t)0x0000C000)
 
#define GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)
 
#define GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)
 
#define GPIO_MODER_MODER8   ((uint32_t)0x00030000)
 
#define GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)
 
#define GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)
 
#define GPIO_MODER_MODER9   ((uint32_t)0x000C0000)
 
#define GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)
 
#define GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)
 
#define GPIO_MODER_MODER10   ((uint32_t)0x00300000)
 
#define GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)
 
#define GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)
 
#define GPIO_MODER_MODER11   ((uint32_t)0x00C00000)
 
#define GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)
 
#define GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)
 
#define GPIO_MODER_MODER12   ((uint32_t)0x03000000)
 
#define GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)
 
#define GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)
 
#define GPIO_MODER_MODER13   ((uint32_t)0x0C000000)
 
#define GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)
 
#define GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)
 
#define GPIO_MODER_MODER14   ((uint32_t)0x30000000)
 
#define GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)
 
#define GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)
 
#define GPIO_MODER_MODER15   ((uint32_t)0xC0000000)
 
#define GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)
 
#define GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)
 
#define GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)
 
#define GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)
 
#define GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)
 
#define GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)
 
#define GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)
 
#define GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)
 
#define GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)
 
#define GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)
 
#define GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)
 
#define GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)
 
#define GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)
 
#define GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)
 
#define GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)
 
#define GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)
 
#define GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)
 
#define GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)
 
#define GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)
 
#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
 
#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
 
#define GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)
 
#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
 
#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
 
#define GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)
 
#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
 
#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
 
#define GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)
 
#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
 
#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
 
#define GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)
 
#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
 
#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
 
#define GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)
 
#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
 
#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
 
#define GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)
 
#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
 
#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
 
#define GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)
 
#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
 
#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
 
#define GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)
 
#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
 
#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
 
#define GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)
 
#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
 
#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
 
#define GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)
 
#define GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)
 
#define GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)
 
#define GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)
 
#define GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)
 
#define GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)
 
#define GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)
 
#define GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)
 
#define GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)
 
#define GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)
 
#define GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)
 
#define GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)
 
#define GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)
 
#define GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)
 
#define GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)
 
#define GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)
 
#define GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)
 
#define GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)
 
#define GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)
 
#define GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)
 
#define GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)
 
#define GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)
 
#define GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)
 
#define GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)
 
#define GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)
 
#define GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)
 
#define GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)
 
#define GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)
 
#define GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)
 
#define GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)
 
#define GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)
 
#define GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)
 
#define GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)
 
#define GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)
 
#define GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)
 
#define GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)
 
#define GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)
 
#define GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)
 
#define GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)
 
#define GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)
 
#define GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)
 
#define GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)
 
#define GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)
 
#define GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)
 
#define GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)
 
#define GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)
 
#define GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)
 
#define GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)
 
#define GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)
 
#define GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)
 
#define GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)
 
#define GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)
 
#define GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)
 
#define GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)
 
#define GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)
 
#define GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)
 
#define GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)
 
#define GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)
 
#define GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)
 
#define GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)
 
#define GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)
 
#define GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)
 
#define GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)
 
#define GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)
 
#define GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)
 
#define GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)
 
#define GPIO_IDR_IDR_0   ((uint32_t)0x00000001)
 
#define GPIO_IDR_IDR_1   ((uint32_t)0x00000002)
 
#define GPIO_IDR_IDR_2   ((uint32_t)0x00000004)
 
#define GPIO_IDR_IDR_3   ((uint32_t)0x00000008)
 
#define GPIO_IDR_IDR_4   ((uint32_t)0x00000010)
 
#define GPIO_IDR_IDR_5   ((uint32_t)0x00000020)
 
#define GPIO_IDR_IDR_6   ((uint32_t)0x00000040)
 
#define GPIO_IDR_IDR_7   ((uint32_t)0x00000080)
 
#define GPIO_IDR_IDR_8   ((uint32_t)0x00000100)
 
#define GPIO_IDR_IDR_9   ((uint32_t)0x00000200)
 
#define GPIO_IDR_IDR_10   ((uint32_t)0x00000400)
 
#define GPIO_IDR_IDR_11   ((uint32_t)0x00000800)
 
#define GPIO_IDR_IDR_12   ((uint32_t)0x00001000)
 
#define GPIO_IDR_IDR_13   ((uint32_t)0x00002000)
 
#define GPIO_IDR_IDR_14   ((uint32_t)0x00004000)
 
#define GPIO_IDR_IDR_15   ((uint32_t)0x00008000)
 
#define GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0
 
#define GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1
 
#define GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2
 
#define GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3
 
#define GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4
 
#define GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5
 
#define GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6
 
#define GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7
 
#define GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8
 
#define GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9
 
#define GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10
 
#define GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11
 
#define GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12
 
#define GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13
 
#define GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14
 
#define GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15
 
#define GPIO_ODR_ODR_0   ((uint32_t)0x00000001)
 
#define GPIO_ODR_ODR_1   ((uint32_t)0x00000002)
 
#define GPIO_ODR_ODR_2   ((uint32_t)0x00000004)
 
#define GPIO_ODR_ODR_3   ((uint32_t)0x00000008)
 
#define GPIO_ODR_ODR_4   ((uint32_t)0x00000010)
 
#define GPIO_ODR_ODR_5   ((uint32_t)0x00000020)
 
#define GPIO_ODR_ODR_6   ((uint32_t)0x00000040)
 
#define GPIO_ODR_ODR_7   ((uint32_t)0x00000080)
 
#define GPIO_ODR_ODR_8   ((uint32_t)0x00000100)
 
#define GPIO_ODR_ODR_9   ((uint32_t)0x00000200)
 
#define GPIO_ODR_ODR_10   ((uint32_t)0x00000400)
 
#define GPIO_ODR_ODR_11   ((uint32_t)0x00000800)
 
#define GPIO_ODR_ODR_12   ((uint32_t)0x00001000)
 
#define GPIO_ODR_ODR_13   ((uint32_t)0x00002000)
 
#define GPIO_ODR_ODR_14   ((uint32_t)0x00004000)
 
#define GPIO_ODR_ODR_15   ((uint32_t)0x00008000)
 
#define GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0
 
#define GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1
 
#define GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2
 
#define GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3
 
#define GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4
 
#define GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5
 
#define GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6
 
#define GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7
 
#define GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8
 
#define GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9
 
#define GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10
 
#define GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11
 
#define GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12
 
#define GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13
 
#define GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14
 
#define GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15
 
#define GPIO_BSRR_BS_0   ((uint32_t)0x00000001)
 
#define GPIO_BSRR_BS_1   ((uint32_t)0x00000002)
 
#define GPIO_BSRR_BS_2   ((uint32_t)0x00000004)
 
#define GPIO_BSRR_BS_3   ((uint32_t)0x00000008)
 
#define GPIO_BSRR_BS_4   ((uint32_t)0x00000010)
 
#define GPIO_BSRR_BS_5   ((uint32_t)0x00000020)
 
#define GPIO_BSRR_BS_6   ((uint32_t)0x00000040)
 
#define GPIO_BSRR_BS_7   ((uint32_t)0x00000080)
 
#define GPIO_BSRR_BS_8   ((uint32_t)0x00000100)
 
#define GPIO_BSRR_BS_9   ((uint32_t)0x00000200)
 
#define GPIO_BSRR_BS_10   ((uint32_t)0x00000400)
 
#define GPIO_BSRR_BS_11   ((uint32_t)0x00000800)
 
#define GPIO_BSRR_BS_12   ((uint32_t)0x00001000)
 
#define GPIO_BSRR_BS_13   ((uint32_t)0x00002000)
 
#define GPIO_BSRR_BS_14   ((uint32_t)0x00004000)
 
#define GPIO_BSRR_BS_15   ((uint32_t)0x00008000)
 
#define GPIO_BSRR_BR_0   ((uint32_t)0x00010000)
 
#define GPIO_BSRR_BR_1   ((uint32_t)0x00020000)
 
#define GPIO_BSRR_BR_2   ((uint32_t)0x00040000)
 
#define GPIO_BSRR_BR_3   ((uint32_t)0x00080000)
 
#define GPIO_BSRR_BR_4   ((uint32_t)0x00100000)
 
#define GPIO_BSRR_BR_5   ((uint32_t)0x00200000)
 
#define GPIO_BSRR_BR_6   ((uint32_t)0x00400000)
 
#define GPIO_BSRR_BR_7   ((uint32_t)0x00800000)
 
#define GPIO_BSRR_BR_8   ((uint32_t)0x01000000)
 
#define GPIO_BSRR_BR_9   ((uint32_t)0x02000000)
 
#define GPIO_BSRR_BR_10   ((uint32_t)0x04000000)
 
#define GPIO_BSRR_BR_11   ((uint32_t)0x08000000)
 
#define GPIO_BSRR_BR_12   ((uint32_t)0x10000000)
 
#define GPIO_BSRR_BR_13   ((uint32_t)0x20000000)
 
#define GPIO_BSRR_BR_14   ((uint32_t)0x40000000)
 
#define GPIO_BSRR_BR_15   ((uint32_t)0x80000000)
 
#define HASH_CR_INIT   ((uint32_t)0x00000004)
 
#define HASH_CR_DMAE   ((uint32_t)0x00000008)
 
#define HASH_CR_DATATYPE   ((uint32_t)0x00000030)
 
#define HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)
 
#define HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)
 
#define HASH_CR_MODE   ((uint32_t)0x00000040)
 
#define HASH_CR_ALGO   ((uint32_t)0x00000080)
 
#define HASH_CR_NBW   ((uint32_t)0x00000F00)
 
#define HASH_CR_NBW_0   ((uint32_t)0x00000100)
 
#define HASH_CR_NBW_1   ((uint32_t)0x00000200)
 
#define HASH_CR_NBW_2   ((uint32_t)0x00000400)
 
#define HASH_CR_NBW_3   ((uint32_t)0x00000800)
 
#define HASH_CR_DINNE   ((uint32_t)0x00001000)
 
#define HASH_CR_LKEY   ((uint32_t)0x00010000)
 
#define HASH_STR_NBW   ((uint32_t)0x0000001F)
 
#define HASH_STR_NBW_0   ((uint32_t)0x00000001)
 
#define HASH_STR_NBW_1   ((uint32_t)0x00000002)
 
#define HASH_STR_NBW_2   ((uint32_t)0x00000004)
 
#define HASH_STR_NBW_3   ((uint32_t)0x00000008)
 
#define HASH_STR_NBW_4   ((uint32_t)0x00000010)
 
#define HASH_STR_DCAL   ((uint32_t)0x00000100)
 
#define HASH_IMR_DINIM   ((uint32_t)0x00000001)
 
#define HASH_IMR_DCIM   ((uint32_t)0x00000002)
 
#define HASH_SR_DINIS   ((uint32_t)0x00000001)
 
#define HASH_SR_DCIS   ((uint32_t)0x00000002)
 
#define HASH_SR_DMAS   ((uint32_t)0x00000004)
 
#define HASH_SR_BUSY   ((uint32_t)0x00000008)
 
#define I2C_CR1_PE   ((uint16_t)0x0001)
 
#define I2C_CR1_SMBUS   ((uint16_t)0x0002)
 
#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
 
#define I2C_CR1_ENARP   ((uint16_t)0x0010)
 
#define I2C_CR1_ENPEC   ((uint16_t)0x0020)
 
#define I2C_CR1_ENGC   ((uint16_t)0x0040)
 
#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
 
#define I2C_CR1_START   ((uint16_t)0x0100)
 
#define I2C_CR1_STOP   ((uint16_t)0x0200)
 
#define I2C_CR1_ACK   ((uint16_t)0x0400)
 
#define I2C_CR1_POS   ((uint16_t)0x0800)
 
#define I2C_CR1_PEC   ((uint16_t)0x1000)
 
#define I2C_CR1_ALERT   ((uint16_t)0x2000)
 
#define I2C_CR1_SWRST   ((uint16_t)0x8000)
 
#define I2C_CR2_FREQ   ((uint16_t)0x003F)
 
#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)
 
#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)
 
#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)
 
#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)
 
#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)
 
#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)
 
#define I2C_CR2_ITERREN   ((uint16_t)0x0100)
 
#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
 
#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
 
#define I2C_CR2_DMAEN   ((uint16_t)0x0800)
 
#define I2C_CR2_LAST   ((uint16_t)0x1000)
 
#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
 
#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
 
#define I2C_OAR1_ADD0   ((uint16_t)0x0001)
 
#define I2C_OAR1_ADD1   ((uint16_t)0x0002)
 
#define I2C_OAR1_ADD2   ((uint16_t)0x0004)
 
#define I2C_OAR1_ADD3   ((uint16_t)0x0008)
 
#define I2C_OAR1_ADD4   ((uint16_t)0x0010)
 
#define I2C_OAR1_ADD5   ((uint16_t)0x0020)
 
#define I2C_OAR1_ADD6   ((uint16_t)0x0040)
 
#define I2C_OAR1_ADD7   ((uint16_t)0x0080)
 
#define I2C_OAR1_ADD8   ((uint16_t)0x0100)
 
#define I2C_OAR1_ADD9   ((uint16_t)0x0200)
 
#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
 
#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)
 
#define I2C_OAR2_ADD2   ((uint8_t)0xFE)
 
#define I2C_DR_DR   ((uint8_t)0xFF)
 
#define I2C_SR1_SB   ((uint16_t)0x0001)
 
#define I2C_SR1_ADDR   ((uint16_t)0x0002)
 
#define I2C_SR1_BTF   ((uint16_t)0x0004)
 
#define I2C_SR1_ADD10   ((uint16_t)0x0008)
 
#define I2C_SR1_STOPF   ((uint16_t)0x0010)
 
#define I2C_SR1_RXNE   ((uint16_t)0x0040)
 
#define I2C_SR1_TXE   ((uint16_t)0x0080)
 
#define I2C_SR1_BERR   ((uint16_t)0x0100)
 
#define I2C_SR1_ARLO   ((uint16_t)0x0200)
 
#define I2C_SR1_AF   ((uint16_t)0x0400)
 
#define I2C_SR1_OVR   ((uint16_t)0x0800)
 
#define I2C_SR1_PECERR   ((uint16_t)0x1000)
 
#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
 
#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)
 
#define I2C_SR2_MSL   ((uint16_t)0x0001)
 
#define I2C_SR2_BUSY   ((uint16_t)0x0002)
 
#define I2C_SR2_TRA   ((uint16_t)0x0004)
 
#define I2C_SR2_GENCALL   ((uint16_t)0x0010)
 
#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
 
#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)
 
#define I2C_SR2_DUALF   ((uint16_t)0x0080)
 
#define I2C_SR2_PEC   ((uint16_t)0xFF00)
 
#define I2C_CCR_CCR   ((uint16_t)0x0FFF)
 
#define I2C_CCR_DUTY   ((uint16_t)0x4000)
 
#define I2C_CCR_FS   ((uint16_t)0x8000)
 
#define I2C_TRISE_TRISE   ((uint8_t)0x3F)
 
#define IWDG_KR_KEY   ((uint16_t)0xFFFF)
 
#define IWDG_PR_PR   ((uint8_t)0x07)
 
#define IWDG_PR_PR_0   ((uint8_t)0x01)
 
#define IWDG_PR_PR_1   ((uint8_t)0x02)
 
#define IWDG_PR_PR_2   ((uint8_t)0x04)
 
#define IWDG_RLR_RL   ((uint16_t)0x0FFF)
 
#define IWDG_SR_PVU   ((uint8_t)0x01)
 
#define IWDG_SR_RVU   ((uint8_t)0x02)
 
#define PWR_CR_LPDS   ((uint16_t)0x0001)
 
#define PWR_CR_PDDS   ((uint16_t)0x0002)
 
#define PWR_CR_CWUF   ((uint16_t)0x0004)
 
#define PWR_CR_CSBF   ((uint16_t)0x0008)
 
#define PWR_CR_PVDE   ((uint16_t)0x0010)
 
#define PWR_CR_PLS   ((uint16_t)0x00E0)
 
#define PWR_CR_PLS_0   ((uint16_t)0x0020)
 
#define PWR_CR_PLS_1   ((uint16_t)0x0040)
 
#define PWR_CR_PLS_2   ((uint16_t)0x0080)
 
#define PWR_CR_PLS_LEV0   ((uint16_t)0x0000)
 
#define PWR_CR_PLS_LEV1   ((uint16_t)0x0020)
 
#define PWR_CR_PLS_LEV2   ((uint16_t)0x0040)
 
#define PWR_CR_PLS_LEV3   ((uint16_t)0x0060)
 
#define PWR_CR_PLS_LEV4   ((uint16_t)0x0080)
 
#define PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)
 
#define PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)
 
#define PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)
 
#define PWR_CR_DBP   ((uint16_t)0x0100)
 
#define PWR_CR_FPDS   ((uint16_t)0x0200)
 
#define PWR_CR_VOS   ((uint16_t)0x4000)
 
#define PWR_CR_PMODE   PWR_CR_VOS
 
#define PWR_CSR_WUF   ((uint16_t)0x0001)
 
#define PWR_CSR_SBF   ((uint16_t)0x0002)
 
#define PWR_CSR_PVDO   ((uint16_t)0x0004)
 
#define PWR_CSR_BRR   ((uint16_t)0x0008)
 
#define PWR_CSR_EWUP   ((uint16_t)0x0100)
 
#define PWR_CSR_BRE   ((uint16_t)0x0200)
 
#define PWR_CSR_VOSRDY   ((uint16_t)0x4000)
 
#define PWR_CSR_REGRDY   PWR_CSR_VOSRDY
 
#define RCC_CR_HSION   ((uint32_t)0x00000001)
 
#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)
 
#define RCC_CR_HSITRIM   ((uint32_t)0x000000F8)
 
#define RCC_CR_HSITRIM_0   ((uint32_t)0x00000008
 
#define RCC_CR_HSITRIM_1   ((uint32_t)0x00000010
 
#define RCC_CR_HSITRIM_2   ((uint32_t)0x00000020
 
#define RCC_CR_HSITRIM_3   ((uint32_t)0x00000040
 
#define RCC_CR_HSITRIM_4   ((uint32_t)0x00000080
 
#define RCC_CR_HSICAL   ((uint32_t)0x0000FF00)
 
#define RCC_CR_HSICAL_0   ((uint32_t)0x00000100
 
#define RCC_CR_HSICAL_1   ((uint32_t)0x00000200
 
#define RCC_CR_HSICAL_2   ((uint32_t)0x00000400
 
#define RCC_CR_HSICAL_3   ((uint32_t)0x00000800
 
#define RCC_CR_HSICAL_4   ((uint32_t)0x00001000
 
#define RCC_CR_HSICAL_5   ((uint32_t)0x00002000
 
#define RCC_CR_HSICAL_6   ((uint32_t)0x00004000
 
#define RCC_CR_HSICAL_7   ((uint32_t)0x00008000
 
#define RCC_CR_HSEON   ((uint32_t)0x00010000)
 
#define RCC_CR_HSERDY   ((uint32_t)0x00020000)
 
#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)
 
#define RCC_CR_CSSON   ((uint32_t)0x00080000)
 
#define RCC_CR_PLLON   ((uint32_t)0x01000000)
 
#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)
 
#define RCC_CR_PLLI2SON   ((uint32_t)0x04000000)
 
#define RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)
 
#define RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)
 
#define RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)
 
#define RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)
 
#define RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)
 
#define RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)
 
#define RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)
 
#define RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)
 
#define RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)
 
#define RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)
 
#define RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)
 
#define RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)
 
#define RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)
 
#define RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)
 
#define RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)
 
#define RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)
 
#define RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)
 
#define RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)
 
#define RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)
 
#define RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)
 
#define RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)
 
#define RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)
 
#define RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)
 
#define RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)
 
#define RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)
 
#define RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)
 
#define RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)
 
#define RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)
 
#define RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)
 
#define RCC_CFGR_SW   ((uint32_t)0x00000003)
 
#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)
 
#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)
 
#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)
 
#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)
 
#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)
 
#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)
 
#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
 
#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
 
#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)
 
#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)
 
#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)
 
#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
 
#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
 
#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
 
#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
 
#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
 
#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
 
#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
 
#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
 
#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
 
#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
 
#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
 
#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
 
#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
 
#define RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)
 
#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)
 
#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)
 
#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)
 
#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)
 
#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)
 
#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)
 
#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)
 
#define RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)
 
#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)
 
#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)
 
#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)
 
#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)
 
#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)
 
#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)
 
#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E000)
 
#define RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)
 
#define RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)
 
#define RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)
 
#define RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)
 
#define RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)
 
#define RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)
 
#define RCC_CFGR_MCO1   ((uint32_t)0x00600000)
 
#define RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)
 
#define RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)
 
#define RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)
 
#define RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)
 
#define RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)
 
#define RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)
 
#define RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)
 
#define RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)
 
#define RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)
 
#define RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)
 
#define RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)
 
#define RCC_CFGR_MCO2   ((uint32_t)0xC0000000)
 
#define RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)
 
#define RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)
 
#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)
 
#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)
 
#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)
 
#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)
 
#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)
 
#define RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)
 
#define RCC_CIR_CSSF   ((uint32_t)0x00000080)
 
#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)
 
#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)
 
#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)
 
#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)
 
#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)
 
#define RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)
 
#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)
 
#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)
 
#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)
 
#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)
 
#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)
 
#define RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)
 
#define RCC_CIR_CSSC   ((uint32_t)0x00800000)
 
#define RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)
 
#define RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)
 
#define RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)
 
#define RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)
 
#define RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)
 
#define RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)
 
#define RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)
 
#define RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)
 
#define RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)
 
#define RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)
 
#define RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)
 
#define RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)
 
#define RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)
 
#define RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)
 
#define RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)
 
#define RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)
 
#define RCC_AHB2RSTR_HSAHRST   ((uint32_t)0x00000020)
 
#define RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)
 
#define RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)
 
#define RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)
 
#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)
 
#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)
 
#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)
 
#define RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)
 
#define RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)
 
#define RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)
 
#define RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)
 
#define RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)
 
#define RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)
 
#define RCC_APB1RSTR_WWDGEN   ((uint32_t)0x00000800)
 
#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00008000)
 
#define RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00010000)
 
#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)
 
#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)
 
#define RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)
 
#define RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)
 
#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)
 
#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)
 
#define RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)
 
#define RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)
 
#define RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)
 
#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)
 
#define RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)
 
#define RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)
 
#define RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)
 
#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)
 
#define RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)
 
#define RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)
 
#define RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)
 
#define RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)
 
#define RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)
 
#define RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)
 
#define RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)
 
#define RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)
 
#define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST
 
#define RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)
 
#define RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)
 
#define RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)
 
#define RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)
 
#define RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)
 
#define RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)
 
#define RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)
 
#define RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)
 
#define RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)
 
#define RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)
 
#define RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)
 
#define RCC_AHB1ENR_CCMDATARAMEN   ((uint32_t)0x00100000)
 
#define RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)
 
#define RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)
 
#define RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)
 
#define RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)
 
#define RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)
 
#define RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)
 
#define RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)
 
#define RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)
 
#define RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)
 
#define RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)
 
#define RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)
 
#define RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)
 
#define RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)
 
#define RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)
 
#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)
 
#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)
 
#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)
 
#define RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)
 
#define RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)
 
#define RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)
 
#define RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)
 
#define RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)
 
#define RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)
 
#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)
 
#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)
 
#define RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)
 
#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)
 
#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)
 
#define RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)
 
#define RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)
 
#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)
 
#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)
 
#define RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)
 
#define RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)
 
#define RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)
 
#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)
 
#define RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)
 
#define RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)
 
#define RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)
 
#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)
 
#define RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)
 
#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)
 
#define RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)
 
#define RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)
 
#define RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)
 
#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)
 
#define RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)
 
#define RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)
 
#define RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)
 
#define RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)
 
#define RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)
 
#define RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)
 
#define RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)
 
#define RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)
 
#define RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)
 
#define RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)
 
#define RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)
 
#define RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)
 
#define RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)
 
#define RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)
 
#define RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)
 
#define RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)
 
#define RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)
 
#define RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)
 
#define RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)
 
#define RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)
 
#define RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)
 
#define RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)
 
#define RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)
 
#define RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)
 
#define RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)
 
#define RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)
 
#define RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)
 
#define RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)
 
#define RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)
 
#define RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)
 
#define RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)
 
#define RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)
 
#define RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)
 
#define RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)
 
#define RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)
 
#define RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)
 
#define RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)
 
#define RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)
 
#define RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)
 
#define RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)
 
#define RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)
 
#define RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)
 
#define RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)
 
#define RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)
 
#define RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)
 
#define RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)
 
#define RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)
 
#define RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)
 
#define RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)
 
#define RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)
 
#define RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)
 
#define RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)
 
#define RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)
 
#define RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)
 
#define RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)
 
#define RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)
 
#define RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)
 
#define RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)
 
#define RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)
 
#define RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)
 
#define RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)
 
#define RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)
 
#define RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)
 
#define RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)
 
#define RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)
 
#define RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)
 
#define RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)
 
#define RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)
 
#define RCC_BDCR_LSEON   ((uint32_t)0x00000001)
 
#define RCC_BDCR_LSERDY   ((uint32_t)0x00000002)
 
#define RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)
 
#define RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)
 
#define RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)
 
#define RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)
 
#define RCC_BDCR_RTCEN   ((uint32_t)0x00008000)
 
#define RCC_BDCR_BDRST   ((uint32_t)0x00010000)
 
#define RCC_CSR_LSION   ((uint32_t)0x00000001)
 
#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)
 
#define RCC_CSR_RMVF   ((uint32_t)0x01000000)
 
#define RCC_CSR_BORRSTF   ((uint32_t)0x02000000)
 
#define RCC_CSR_PADRSTF   ((uint32_t)0x04000000)
 
#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)
 
#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)
 
#define RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)
 
#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)
 
#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)
 
#define RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)
 
#define RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)
 
#define RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)
 
#define RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)
 
#define RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)
 
#define RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)
 
#define RNG_CR_RNGEN   ((uint32_t)0x00000004)
 
#define RNG_CR_IE   ((uint32_t)0x00000008)
 
#define RNG_SR_DRDY   ((uint32_t)0x00000001)
 
#define RNG_SR_CECS   ((uint32_t)0x00000002)
 
#define RNG_SR_SECS   ((uint32_t)0x00000004)
 
#define RNG_SR_CEIS   ((uint32_t)0x00000020)
 
#define RNG_SR_SEIS   ((uint32_t)0x00000040)
 
#define RTC_TR_PM   ((uint32_t)0x00400000)
 
#define RTC_TR_HT   ((uint32_t)0x00300000)
 
#define RTC_TR_HT_0   ((uint32_t)0x00100000)
 
#define RTC_TR_HT_1   ((uint32_t)0x00200000)
 
#define RTC_TR_HU   ((uint32_t)0x000F0000)
 
#define RTC_TR_HU_0   ((uint32_t)0x00010000)
 
#define RTC_TR_HU_1   ((uint32_t)0x00020000)
 
#define RTC_TR_HU_2   ((uint32_t)0x00040000)
 
#define RTC_TR_HU_3   ((uint32_t)0x00080000)
 
#define RTC_TR_MNT   ((uint32_t)0x00007000)
 
#define RTC_TR_MNT_0   ((uint32_t)0x00001000)
 
#define RTC_TR_MNT_1   ((uint32_t)0x00002000)
 
#define RTC_TR_MNT_2   ((uint32_t)0x00004000)
 
#define RTC_TR_MNU   ((uint32_t)0x00000F00)
 
#define RTC_TR_MNU_0   ((uint32_t)0x00000100)
 
#define RTC_TR_MNU_1   ((uint32_t)0x00000200)
 
#define RTC_TR_MNU_2   ((uint32_t)0x00000400)
 
#define RTC_TR_MNU_3   ((uint32_t)0x00000800)
 
#define RTC_TR_ST   ((uint32_t)0x00000070)
 
#define RTC_TR_ST_0   ((uint32_t)0x00000010)
 
#define RTC_TR_ST_1   ((uint32_t)0x00000020)
 
#define RTC_TR_ST_2   ((uint32_t)0x00000040)
 
#define RTC_TR_SU   ((uint32_t)0x0000000F)
 
#define RTC_TR_SU_0   ((uint32_t)0x00000001)
 
#define RTC_TR_SU_1   ((uint32_t)0x00000002)
 
#define RTC_TR_SU_2   ((uint32_t)0x00000004)
 
#define RTC_TR_SU_3   ((uint32_t)0x00000008)
 
#define RTC_DR_YT   ((uint32_t)0x00F00000)
 
#define RTC_DR_YT_0   ((uint32_t)0x00100000)
 
#define RTC_DR_YT_1   ((uint32_t)0x00200000)
 
#define RTC_DR_YT_2   ((uint32_t)0x00400000)
 
#define RTC_DR_YT_3   ((uint32_t)0x00800000)
 
#define RTC_DR_YU   ((uint32_t)0x000F0000)
 
#define RTC_DR_YU_0   ((uint32_t)0x00010000)
 
#define RTC_DR_YU_1   ((uint32_t)0x00020000)
 
#define RTC_DR_YU_2   ((uint32_t)0x00040000)
 
#define RTC_DR_YU_3   ((uint32_t)0x00080000)
 
#define RTC_DR_WDU   ((uint32_t)0x0000E000)
 
#define RTC_DR_WDU_0   ((uint32_t)0x00002000)
 
#define RTC_DR_WDU_1   ((uint32_t)0x00004000)
 
#define RTC_DR_WDU_2   ((uint32_t)0x00008000)
 
#define RTC_DR_MT   ((uint32_t)0x00001000)
 
#define RTC_DR_MU   ((uint32_t)0x00000F00)
 
#define RTC_DR_MU_0   ((uint32_t)0x00000100)
 
#define RTC_DR_MU_1   ((uint32_t)0x00000200)
 
#define RTC_DR_MU_2   ((uint32_t)0x00000400)
 
#define RTC_DR_MU_3   ((uint32_t)0x00000800)
 
#define RTC_DR_DT   ((uint32_t)0x00000030)
 
#define RTC_DR_DT_0   ((uint32_t)0x00000010)
 
#define RTC_DR_DT_1   ((uint32_t)0x00000020)
 
#define RTC_DR_DU   ((uint32_t)0x0000000F)
 
#define RTC_DR_DU_0   ((uint32_t)0x00000001)
 
#define RTC_DR_DU_1   ((uint32_t)0x00000002)
 
#define RTC_DR_DU_2   ((uint32_t)0x00000004)
 
#define RTC_DR_DU_3   ((uint32_t)0x00000008)
 
#define RTC_CR_COE   ((uint32_t)0x00800000)
 
#define RTC_CR_OSEL   ((uint32_t)0x00600000)
 
#define RTC_CR_OSEL_0   ((uint32_t)0x00200000)
 
#define RTC_CR_OSEL_1   ((uint32_t)0x00400000)
 
#define RTC_CR_POL   ((uint32_t)0x00100000)
 
#define RTC_CR_COSEL   ((uint32_t)0x00080000)
 
#define RTC_CR_BCK   ((uint32_t)0x00040000)
 
#define RTC_CR_SUB1H   ((uint32_t)0x00020000)
 
#define RTC_CR_ADD1H   ((uint32_t)0x00010000)
 
#define RTC_CR_TSIE   ((uint32_t)0x00008000)
 
#define RTC_CR_WUTIE   ((uint32_t)0x00004000)
 
#define RTC_CR_ALRBIE   ((uint32_t)0x00002000)
 
#define RTC_CR_ALRAIE   ((uint32_t)0x00001000)
 
#define RTC_CR_TSE   ((uint32_t)0x00000800)
 
#define RTC_CR_WUTE   ((uint32_t)0x00000400)
 
#define RTC_CR_ALRBE   ((uint32_t)0x00000200)
 
#define RTC_CR_ALRAE   ((uint32_t)0x00000100)
 
#define RTC_CR_DCE   ((uint32_t)0x00000080)
 
#define RTC_CR_FMT   ((uint32_t)0x00000040)
 
#define RTC_CR_BYPSHAD   ((uint32_t)0x00000020)
 
#define RTC_CR_REFCKON   ((uint32_t)0x00000010)
 
#define RTC_CR_TSEDGE   ((uint32_t)0x00000008)
 
#define RTC_CR_WUCKSEL   ((uint32_t)0x00000007)
 
#define RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)
 
#define RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)
 
#define RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)
 
#define RTC_ISR_RECALPF   ((uint32_t)0x00010000)
 
#define RTC_ISR_TAMP1F   ((uint32_t)0x00002000)
 
#define RTC_ISR_TSOVF   ((uint32_t)0x00001000)
 
#define RTC_ISR_TSF   ((uint32_t)0x00000800)
 
#define RTC_ISR_WUTF   ((uint32_t)0x00000400)
 
#define RTC_ISR_ALRBF   ((uint32_t)0x00000200)
 
#define RTC_ISR_ALRAF   ((uint32_t)0x00000100)
 
#define RTC_ISR_INIT   ((uint32_t)0x00000080)
 
#define RTC_ISR_INITF   ((uint32_t)0x00000040)
 
#define RTC_ISR_RSF   ((uint32_t)0x00000020)
 
#define RTC_ISR_INITS   ((uint32_t)0x00000010)
 
#define RTC_ISR_SHPF   ((uint32_t)0x00000008)
 
#define RTC_ISR_WUTWF   ((uint32_t)0x00000004)
 
#define RTC_ISR_ALRBWF   ((uint32_t)0x00000002)
 
#define RTC_ISR_ALRAWF   ((uint32_t)0x00000001)
 
#define RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)
 
#define RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)
 
#define RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)
 
#define RTC_CALIBR_DCS   ((uint32_t)0x00000080)
 
#define RTC_CALIBR_DC   ((uint32_t)0x0000001F)
 
#define RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)
 
#define RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)
 
#define RTC_ALRMAR_DT   ((uint32_t)0x30000000)
 
#define RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)
 
#define RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)
 
#define RTC_ALRMAR_DU   ((uint32_t)0x0F000000)
 
#define RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)
 
#define RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)
 
#define RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)
 
#define RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)
 
#define RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)
 
#define RTC_ALRMAR_PM   ((uint32_t)0x00400000)
 
#define RTC_ALRMAR_HT   ((uint32_t)0x00300000)
 
#define RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)
 
#define RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)
 
#define RTC_ALRMAR_HU   ((uint32_t)0x000F0000)
 
#define RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)
 
#define RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)
 
#define RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)
 
#define RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)
 
#define RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)
 
#define RTC_ALRMAR_MNT   ((uint32_t)0x00007000)
 
#define RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)
 
#define RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)
 
#define RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)
 
#define RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)
 
#define RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)
 
#define RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)
 
#define RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)
 
#define RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)
 
#define RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)
 
#define RTC_ALRMAR_ST   ((uint32_t)0x00000070)
 
#define RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)
 
#define RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)
 
#define RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)
 
#define RTC_ALRMAR_SU   ((uint32_t)0x0000000F)
 
#define RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)
 
#define RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)
 
#define RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)
 
#define RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)
 
#define RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)
 
#define RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)
 
#define RTC_ALRMBR_DT   ((uint32_t)0x30000000)
 
#define RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)
 
#define RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)
 
#define RTC_ALRMBR_DU   ((uint32_t)0x0F000000)
 
#define RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)
 
#define RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)
 
#define RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)
 
#define RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)
 
#define RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)
 
#define RTC_ALRMBR_PM   ((uint32_t)0x00400000)
 
#define RTC_ALRMBR_HT   ((uint32_t)0x00300000)
 
#define RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)
 
#define RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)
 
#define RTC_ALRMBR_HU   ((uint32_t)0x000F0000)
 
#define RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)
 
#define RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)
 
#define RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)
 
#define RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)
 
#define RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)
 
#define RTC_ALRMBR_MNT   ((uint32_t)0x00007000)
 
#define RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)
 
#define RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)
 
#define RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)
 
#define RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)
 
#define RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)
 
#define RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)
 
#define RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)
 
#define RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)
 
#define RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)
 
#define RTC_ALRMBR_ST   ((uint32_t)0x00000070)
 
#define RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)
 
#define RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)
 
#define RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)
 
#define RTC_ALRMBR_SU   ((uint32_t)0x0000000F)
 
#define RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)
 
#define RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)
 
#define RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)
 
#define RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)
 
#define RTC_WPR_KEY   ((uint32_t)0x000000FF)
 
#define RTC_SSR_SS   ((uint32_t)0x0000FFFF)
 
#define RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)
 
#define RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)
 
#define RTC_TSTR_PM   ((uint32_t)0x00400000)
 
#define RTC_TSTR_HT   ((uint32_t)0x00300000)
 
#define RTC_TSTR_HT_0   ((uint32_t)0x00100000)
 
#define RTC_TSTR_HT_1   ((uint32_t)0x00200000)
 
#define RTC_TSTR_HU   ((uint32_t)0x000F0000)
 
#define RTC_TSTR_HU_0   ((uint32_t)0x00010000)
 
#define RTC_TSTR_HU_1   ((uint32_t)0x00020000)
 
#define RTC_TSTR_HU_2   ((uint32_t)0x00040000)
 
#define RTC_TSTR_HU_3   ((uint32_t)0x00080000)
 
#define RTC_TSTR_MNT   ((uint32_t)0x00007000)
 
#define RTC_TSTR_MNT_0   ((uint32_t)0x00001000)
 
#define RTC_TSTR_MNT_1   ((uint32_t)0x00002000)
 
#define RTC_TSTR_MNT_2   ((uint32_t)0x00004000)
 
#define RTC_TSTR_MNU   ((uint32_t)0x00000F00)
 
#define RTC_TSTR_MNU_0   ((uint32_t)0x00000100)
 
#define RTC_TSTR_MNU_1   ((uint32_t)0x00000200)
 
#define RTC_TSTR_MNU_2   ((uint32_t)0x00000400)
 
#define RTC_TSTR_MNU_3   ((uint32_t)0x00000800)
 
#define RTC_TSTR_ST   ((uint32_t)0x00000070)
 
#define RTC_TSTR_ST_0   ((uint32_t)0x00000010)
 
#define RTC_TSTR_ST_1   ((uint32_t)0x00000020)
 
#define RTC_TSTR_ST_2   ((uint32_t)0x00000040)
 
#define RTC_TSTR_SU   ((uint32_t)0x0000000F)
 
#define RTC_TSTR_SU_0   ((uint32_t)0x00000001)
 
#define RTC_TSTR_SU_1   ((uint32_t)0x00000002)
 
#define RTC_TSTR_SU_2   ((uint32_t)0x00000004)
 
#define RTC_TSTR_SU_3   ((uint32_t)0x00000008)
 
#define RTC_TSDR_WDU   ((uint32_t)0x0000E000)
 
#define RTC_TSDR_WDU_0   ((uint32_t)0x00002000)
 
#define RTC_TSDR_WDU_1   ((uint32_t)0x00004000)
 
#define RTC_TSDR_WDU_2   ((uint32_t)0x00008000)
 
#define RTC_TSDR_MT   ((uint32_t)0x00001000)
 
#define RTC_TSDR_MU   ((uint32_t)0x00000F00)
 
#define RTC_TSDR_MU_0   ((uint32_t)0x00000100)
 
#define RTC_TSDR_MU_1   ((uint32_t)0x00000200)
 
#define RTC_TSDR_MU_2   ((uint32_t)0x00000400)
 
#define RTC_TSDR_MU_3   ((uint32_t)0x00000800)
 
#define RTC_TSDR_DT   ((uint32_t)0x00000030)
 
#define RTC_TSDR_DT_0   ((uint32_t)0x00000010)
 
#define RTC_TSDR_DT_1   ((uint32_t)0x00000020)
 
#define RTC_TSDR_DU   ((uint32_t)0x0000000F)
 
#define RTC_TSDR_DU_0   ((uint32_t)0x00000001)
 
#define RTC_TSDR_DU_1   ((uint32_t)0x00000002)
 
#define RTC_TSDR_DU_2   ((uint32_t)0x00000004)
 
#define RTC_TSDR_DU_3   ((uint32_t)0x00000008)
 
#define RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)
 
#define RTC_CALR_CALP   ((uint32_t)0x00008000)
 
#define RTC_CALR_CALW8   ((uint32_t)0x00004000)
 
#define RTC_CALR_CALW16   ((uint32_t)0x00002000)
 
#define RTC_CALR_CALM   ((uint32_t)0x000001FF)
 
#define RTC_CALR_CALM_0   ((uint32_t)0x00000001)
 
#define RTC_CALR_CALM_1   ((uint32_t)0x00000002)
 
#define RTC_CALR_CALM_2   ((uint32_t)0x00000004)
 
#define RTC_CALR_CALM_3   ((uint32_t)0x00000008)
 
#define RTC_CALR_CALM_4   ((uint32_t)0x00000010)
 
#define RTC_CALR_CALM_5   ((uint32_t)0x00000020)
 
#define RTC_CALR_CALM_6   ((uint32_t)0x00000040)
 
#define RTC_CALR_CALM_7   ((uint32_t)0x00000080)
 
#define RTC_CALR_CALM_8   ((uint32_t)0x00000100)
 
#define RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)
 
#define RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)
 
#define RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)
 
#define RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)
 
#define RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)
 
#define RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)
 
#define RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)
 
#define RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)
 
#define RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)
 
#define RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)
 
#define RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)
 
#define RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)
 
#define RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)
 
#define RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)
 
#define RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)
 
#define RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)
 
#define RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)
 
#define RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)
 
#define RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)
 
#define RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)
 
#define RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)
 
#define RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)
 
#define RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)
 
#define RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)
 
#define RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)
 
#define RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)
 
#define RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)
 
#define RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)
 
#define RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)
 
#define RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)
 
#define RTC_BKP0R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP1R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP2R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP3R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP4R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP5R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP6R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP7R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP8R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP9R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP10R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP11R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP12R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP13R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP14R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP15R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP16R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP17R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP18R   ((uint32_t)0xFFFFFFFF)
 
#define RTC_BKP19R   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
 
#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
 
#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
 
#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
 
#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
 
#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
 
#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
 
#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
 
#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
 
#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
 
#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
 
#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
 
#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
 
#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
 
#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
 
#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
 
#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)
 
#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
 
#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
 
#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
 
#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
 
#define SDIO_CMD_NIEN   ((uint16_t)0x2000)
 
#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
 
#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
 
#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
 
#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
 
#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
 
#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
 
#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
 
#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
 
#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
 
#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
 
#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
 
#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
 
#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
 
#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
 
#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
 
#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
 
#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
 
#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
 
#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
 
#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
 
#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
 
#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
 
#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
 
#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)
 
#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
 
#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)
 
#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)
 
#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
 
#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)
 
#define SDIO_STA_TXACT   ((uint32_t)0x00001000)
 
#define SDIO_STA_RXACT   ((uint32_t)0x00002000)
 
#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
 
#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
 
#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
 
#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
 
#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
 
#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
 
#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
 
#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
 
#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
 
#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
 
#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
 
#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
 
#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
 
#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
 
#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
 
#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
 
#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
 
#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
 
#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
 
#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
 
#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
 
#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
 
#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
 
#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
 
#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
 
#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
 
#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
 
#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
 
#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
 
#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
 
#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
 
#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
 
#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
 
#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
 
#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
 
#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
 
#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
 
#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
 
#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
 
#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
 
#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
 
#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
 
#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
 
#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
 
#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
 
#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
 
#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
 
#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
 
#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
 
#define SPI_CR1_CPHA   ((uint16_t)0x0001)
 
#define SPI_CR1_CPOL   ((uint16_t)0x0002)
 
#define SPI_CR1_MSTR   ((uint16_t)0x0004)
 
#define SPI_CR1_BR   ((uint16_t)0x0038)
 
#define SPI_CR1_BR_0   ((uint16_t)0x0008)
 
#define SPI_CR1_BR_1   ((uint16_t)0x0010)
 
#define SPI_CR1_BR_2   ((uint16_t)0x0020)
 
#define SPI_CR1_SPE   ((uint16_t)0x0040)
 
#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
 
#define SPI_CR1_SSI   ((uint16_t)0x0100)
 
#define SPI_CR1_SSM   ((uint16_t)0x0200)
 
#define SPI_CR1_RXONLY   ((uint16_t)0x0400)
 
#define SPI_CR1_DFF   ((uint16_t)0x0800)
 
#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
 
#define SPI_CR1_CRCEN   ((uint16_t)0x2000)
 
#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)
 
#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
 
#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)
 
#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)
 
#define SPI_CR2_SSOE   ((uint8_t)0x04)
 
#define SPI_CR2_ERRIE   ((uint8_t)0x20)
 
#define SPI_CR2_RXNEIE   ((uint8_t)0x40)
 
#define SPI_CR2_TXEIE   ((uint8_t)0x80)
 
#define SPI_SR_RXNE   ((uint8_t)0x01)
 
#define SPI_SR_TXE   ((uint8_t)0x02)
 
#define SPI_SR_CHSIDE   ((uint8_t)0x04)
 
#define SPI_SR_UDR   ((uint8_t)0x08)
 
#define SPI_SR_CRCERR   ((uint8_t)0x10)
 
#define SPI_SR_MODF   ((uint8_t)0x20)
 
#define SPI_SR_OVR   ((uint8_t)0x40)
 
#define SPI_SR_BSY   ((uint8_t)0x80)
 
#define SPI_DR_DR   ((uint16_t)0xFFFF)
 
#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
 
#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
 
#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
 
#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
 
#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
 
#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
 
#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
 
#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
 
#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
 
#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
 
#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
 
#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
 
#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
 
#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
 
#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
 
#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
 
#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
 
#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
 
#define SPI_I2SPR_ODD   ((uint16_t)0x0100)
 
#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
 
#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)
 
#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)
 
#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)
 
#define SYSCFG_PMC_MII_RMII_SEL   ((uint32_t)0x00800000)
 
#define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL
 
#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
 EXTI0 configuration

 
#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
 EXTI1 configuration

 
#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
 EXTI2 configuration

 
#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
 EXTI3 configuration

 
#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
 EXTI4 configuration

 
#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
 EXTI5 configuration

 
#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
 EXTI6 configuration

 
#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
 EXTI7 configuration

 
#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
 EXTI8 configuration

 
#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
 EXTI9 configuration

 
#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
 EXTI10 configuration

 
#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
 EXTI11 configuration

 
#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
 EXTI12 configuration

 
#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR3_EXTI12_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
 EXTI13 configuration

 
#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR3_EXTI13_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
 EXTI14 configuration

 
#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR3_EXTI14_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
 EXTI15 configuration

 
#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR3_EXTI15_PH   ((uint16_t)0x7000)
 
#define SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)
 
#define SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)
 
#define TIM_CR1_CEN   ((uint16_t)0x0001)
 
#define TIM_CR1_UDIS   ((uint16_t)0x0002)
 
#define TIM_CR1_URS   ((uint16_t)0x0004)
 
#define TIM_CR1_OPM   ((uint16_t)0x0008)
 
#define TIM_CR1_DIR   ((uint16_t)0x0010)
 
#define TIM_CR1_CMS   ((uint16_t)0x0060)
 
#define TIM_CR1_CMS_0   ((uint16_t)0x0020)
 
#define TIM_CR1_CMS_1   ((uint16_t)0x0040)
 
#define TIM_CR1_ARPE   ((uint16_t)0x0080)
 
#define TIM_CR1_CKD   ((uint16_t)0x0300)
 
#define TIM_CR1_CKD_0   ((uint16_t)0x0100)
 
#define TIM_CR1_CKD_1   ((uint16_t)0x0200)
 
#define TIM_CR2_CCPC   ((uint16_t)0x0001)
 
#define TIM_CR2_CCUS   ((uint16_t)0x0004)
 
#define TIM_CR2_CCDS   ((uint16_t)0x0008)
 
#define TIM_CR2_MMS   ((uint16_t)0x0070)
 
#define TIM_CR2_MMS_0   ((uint16_t)0x0010)
 
#define TIM_CR2_MMS_1   ((uint16_t)0x0020)
 
#define TIM_CR2_MMS_2   ((uint16_t)0x0040)
 
#define TIM_CR2_TI1S   ((uint16_t)0x0080)
 
#define TIM_CR2_OIS1   ((uint16_t)0x0100)
 
#define TIM_CR2_OIS1N   ((uint16_t)0x0200)
 
#define TIM_CR2_OIS2   ((uint16_t)0x0400)
 
#define TIM_CR2_OIS2N   ((uint16_t)0x0800)
 
#define TIM_CR2_OIS3   ((uint16_t)0x1000)
 
#define TIM_CR2_OIS3N   ((uint16_t)0x2000)
 
#define TIM_CR2_OIS4   ((uint16_t)0x4000)
 
#define TIM_SMCR_SMS   ((uint16_t)0x0007)
 
#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)
 
#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)
 
#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)
 
#define TIM_SMCR_TS   ((uint16_t)0x0070)
 
#define TIM_SMCR_TS_0   ((uint16_t)0x0010)
 
#define TIM_SMCR_TS_1   ((uint16_t)0x0020)
 
#define TIM_SMCR_TS_2   ((uint16_t)0x0040)
 
#define TIM_SMCR_MSM   ((uint16_t)0x0080)
 
#define TIM_SMCR_ETF   ((uint16_t)0x0F00)
 
#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)
 
#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)
 
#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)
 
#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)
 
#define TIM_SMCR_ETPS   ((uint16_t)0x3000)
 
#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
 
#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
 
#define TIM_SMCR_ECE   ((uint16_t)0x4000)
 
#define TIM_SMCR_ETP   ((uint16_t)0x8000)
 
#define TIM_DIER_UIE   ((uint16_t)0x0001)
 
#define TIM_DIER_CC1IE   ((uint16_t)0x0002)
 
#define TIM_DIER_CC2IE   ((uint16_t)0x0004)
 
#define TIM_DIER_CC3IE   ((uint16_t)0x0008)
 
#define TIM_DIER_CC4IE   ((uint16_t)0x0010)
 
#define TIM_DIER_COMIE   ((uint16_t)0x0020)
 
#define TIM_DIER_TIE   ((uint16_t)0x0040)
 
#define TIM_DIER_BIE   ((uint16_t)0x0080)
 
#define TIM_DIER_UDE   ((uint16_t)0x0100)
 
#define TIM_DIER_CC1DE   ((uint16_t)0x0200)
 
#define TIM_DIER_CC2DE   ((uint16_t)0x0400)
 
#define TIM_DIER_CC3DE   ((uint16_t)0x0800)
 
#define TIM_DIER_CC4DE   ((uint16_t)0x1000)
 
#define TIM_DIER_COMDE   ((uint16_t)0x2000)
 
#define TIM_DIER_TDE   ((uint16_t)0x4000)
 
#define TIM_SR_UIF   ((uint16_t)0x0001)
 
#define TIM_SR_CC1IF   ((uint16_t)0x0002)
 
#define TIM_SR_CC2IF   ((uint16_t)0x0004)
 
#define TIM_SR_CC3IF   ((uint16_t)0x0008)
 
#define TIM_SR_CC4IF   ((uint16_t)0x0010)
 
#define TIM_SR_COMIF   ((uint16_t)0x0020)
 
#define TIM_SR_TIF   ((uint16_t)0x0040)
 
#define TIM_SR_BIF   ((uint16_t)0x0080)
 
#define TIM_SR_CC1OF   ((uint16_t)0x0200)
 
#define TIM_SR_CC2OF   ((uint16_t)0x0400)
 
#define TIM_SR_CC3OF   ((uint16_t)0x0800)
 
#define TIM_SR_CC4OF   ((uint16_t)0x1000)
 
#define TIM_EGR_UG   ((uint8_t)0x01)
 
#define TIM_EGR_CC1G   ((uint8_t)0x02)
 
#define TIM_EGR_CC2G   ((uint8_t)0x04)
 
#define TIM_EGR_CC3G   ((uint8_t)0x08)
 
#define TIM_EGR_CC4G   ((uint8_t)0x10)
 
#define TIM_EGR_COMG   ((uint8_t)0x20)
 
#define TIM_EGR_TG   ((uint8_t)0x40)
 
#define TIM_EGR_BG   ((uint8_t)0x80)
 
#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)
 
#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
 
#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
 
#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
 
#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
 
#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)
 
#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
 
#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
 
#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
 
#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
 
#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)
 
#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
 
#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
 
#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
 
#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
 
#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)
 
#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
 
#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
 
#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
 
#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
 
#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
 
#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
 
#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
 
#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
 
#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
 
#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
 
#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
 
#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
 
#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
 
#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
 
#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
 
#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)
 
#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
 
#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
 
#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
 
#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
 
#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)
 
#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
 
#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
 
#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
 
#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
 
#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)
 
#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
 
#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
 
#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
 
#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
 
#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)
 
#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
 
#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
 
#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
 
#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
 
#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)
 
#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
 
#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
 
#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
 
#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
 
#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
 
#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
 
#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
 
#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
 
#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
 
#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
 
#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
 
#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
 
#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
 
#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
 
#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
 
#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)
 
#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
 
#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
 
#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
 
#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
 
#define TIM_CCER_CC1E   ((uint16_t)0x0001)
 
#define TIM_CCER_CC1P   ((uint16_t)0x0002)
 
#define TIM_CCER_CC1NE   ((uint16_t)0x0004)
 
#define TIM_CCER_CC1NP   ((uint16_t)0x0008)
 
#define TIM_CCER_CC2E   ((uint16_t)0x0010)
 
#define TIM_CCER_CC2P   ((uint16_t)0x0020)
 
#define TIM_CCER_CC2NE   ((uint16_t)0x0040)
 
#define TIM_CCER_CC2NP   ((uint16_t)0x0080)
 
#define TIM_CCER_CC3E   ((uint16_t)0x0100)
 
#define TIM_CCER_CC3P   ((uint16_t)0x0200)
 
#define TIM_CCER_CC3NE   ((uint16_t)0x0400)
 
#define TIM_CCER_CC3NP   ((uint16_t)0x0800)
 
#define TIM_CCER_CC4E   ((uint16_t)0x1000)
 
#define TIM_CCER_CC4P   ((uint16_t)0x2000)
 
#define TIM_CCER_CC4NP   ((uint16_t)0x8000)
 
#define TIM_CNT_CNT   ((uint16_t)0xFFFF)
 
#define TIM_PSC_PSC   ((uint16_t)0xFFFF)
 
#define TIM_ARR_ARR   ((uint16_t)0xFFFF)
 
#define TIM_RCR_REP   ((uint8_t)0xFF)
 
#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
 
#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
 
#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
 
#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
 
#define TIM_BDTR_DTG   ((uint16_t)0x00FF)
 
#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)
 
#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)
 
#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)
 
#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)
 
#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)
 
#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)
 
#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)
 
#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)
 
#define TIM_BDTR_LOCK   ((uint16_t)0x0300)
 
#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)
 
#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)
 
#define TIM_BDTR_OSSI   ((uint16_t)0x0400)
 
#define TIM_BDTR_OSSR   ((uint16_t)0x0800)
 
#define TIM_BDTR_BKE   ((uint16_t)0x1000)
 
#define TIM_BDTR_BKP   ((uint16_t)0x2000)
 
#define TIM_BDTR_AOE   ((uint16_t)0x4000)
 
#define TIM_BDTR_MOE   ((uint16_t)0x8000)
 
#define TIM_DCR_DBA   ((uint16_t)0x001F)
 
#define TIM_DCR_DBA_0   ((uint16_t)0x0001)
 
#define TIM_DCR_DBA_1   ((uint16_t)0x0002)
 
#define TIM_DCR_DBA_2   ((uint16_t)0x0004)
 
#define TIM_DCR_DBA_3   ((uint16_t)0x0008)
 
#define TIM_DCR_DBA_4   ((uint16_t)0x0010)
 
#define TIM_DCR_DBL   ((uint16_t)0x1F00)
 
#define TIM_DCR_DBL_0   ((uint16_t)0x0100)
 
#define TIM_DCR_DBL_1   ((uint16_t)0x0200)
 
#define TIM_DCR_DBL_2   ((uint16_t)0x0400)
 
#define TIM_DCR_DBL_3   ((uint16_t)0x0800)
 
#define TIM_DCR_DBL_4   ((uint16_t)0x1000)
 
#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
 
#define TIM_OR_TI4_RMP   ((uint16_t)0x00C0)
 
#define TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)
 
#define TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)
 
#define TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)
 
#define TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)
 
#define TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)
 
#define USART_SR_PE   ((uint16_t)0x0001)
 
#define USART_SR_FE   ((uint16_t)0x0002)
 
#define USART_SR_NE   ((uint16_t)0x0004)
 
#define USART_SR_ORE   ((uint16_t)0x0008)
 
#define USART_SR_IDLE   ((uint16_t)0x0010)
 
#define USART_SR_RXNE   ((uint16_t)0x0020)
 
#define USART_SR_TC   ((uint16_t)0x0040)
 
#define USART_SR_TXE   ((uint16_t)0x0080)
 
#define USART_SR_LBD   ((uint16_t)0x0100)
 
#define USART_SR_CTS   ((uint16_t)0x0200)
 
#define USART_DR_DR   ((uint16_t)0x01FF)
 
#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)
 
#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)
 
#define USART_CR1_SBK   ((uint16_t)0x0001)
 
#define USART_CR1_RWU   ((uint16_t)0x0002)
 
#define USART_CR1_RE   ((uint16_t)0x0004)
 
#define USART_CR1_TE   ((uint16_t)0x0008)
 
#define USART_CR1_IDLEIE   ((uint16_t)0x0010)
 
#define USART_CR1_RXNEIE   ((uint16_t)0x0020)
 
#define USART_CR1_TCIE   ((uint16_t)0x0040)
 
#define USART_CR1_TXEIE   ((uint16_t)0x0080)
 
#define USART_CR1_PEIE   ((uint16_t)0x0100)
 
#define USART_CR1_PS   ((uint16_t)0x0200)
 
#define USART_CR1_PCE   ((uint16_t)0x0400)
 
#define USART_CR1_WAKE   ((uint16_t)0x0800)
 
#define USART_CR1_M   ((uint16_t)0x1000)
 
#define USART_CR1_UE   ((uint16_t)0x2000)
 
#define USART_CR1_OVER8   ((uint16_t)0x8000)
 
#define USART_CR2_ADD   ((uint16_t)0x000F)
 
#define USART_CR2_LBDL   ((uint16_t)0x0020)
 
#define USART_CR2_LBDIE   ((uint16_t)0x0040)
 
#define USART_CR2_LBCL   ((uint16_t)0x0100)
 
#define USART_CR2_CPHA   ((uint16_t)0x0200)
 
#define USART_CR2_CPOL   ((uint16_t)0x0400)
 
#define USART_CR2_CLKEN   ((uint16_t)0x0800)
 
#define USART_CR2_STOP   ((uint16_t)0x3000)
 
#define USART_CR2_STOP_0   ((uint16_t)0x1000)
 
#define USART_CR2_STOP_1   ((uint16_t)0x2000)
 
#define USART_CR2_LINEN   ((uint16_t)0x4000)
 
#define USART_CR3_EIE   ((uint16_t)0x0001)
 
#define USART_CR3_IREN   ((uint16_t)0x0002)
 
#define USART_CR3_IRLP   ((uint16_t)0x0004)
 
#define USART_CR3_HDSEL   ((uint16_t)0x0008)
 
#define USART_CR3_NACK   ((uint16_t)0x0010)
 
#define USART_CR3_SCEN   ((uint16_t)0x0020)
 
#define USART_CR3_DMAR   ((uint16_t)0x0040)
 
#define USART_CR3_DMAT   ((uint16_t)0x0080)
 
#define USART_CR3_RTSE   ((uint16_t)0x0100)
 
#define USART_CR3_CTSE   ((uint16_t)0x0200)
 
#define USART_CR3_CTSIE   ((uint16_t)0x0400)
 
#define USART_CR3_ONEBIT   ((uint16_t)0x0800)
 
#define USART_GTPR_PSC   ((uint16_t)0x00FF)
 
#define USART_GTPR_PSC_0   ((uint16_t)0x0001)
 
#define USART_GTPR_PSC_1   ((uint16_t)0x0002)
 
#define USART_GTPR_PSC_2   ((uint16_t)0x0004)
 
#define USART_GTPR_PSC_3   ((uint16_t)0x0008)
 
#define USART_GTPR_PSC_4   ((uint16_t)0x0010)
 
#define USART_GTPR_PSC_5   ((uint16_t)0x0020)
 
#define USART_GTPR_PSC_6   ((uint16_t)0x0040)
 
#define USART_GTPR_PSC_7   ((uint16_t)0x0080)
 
#define USART_GTPR_GT   ((uint16_t)0xFF00)
 
#define WWDG_CR_T   ((uint8_t)0x7F)
 
#define WWDG_CR_T0   ((uint8_t)0x01)
 
#define WWDG_CR_T1   ((uint8_t)0x02)
 
#define WWDG_CR_T2   ((uint8_t)0x04)
 
#define WWDG_CR_T3   ((uint8_t)0x08)
 
#define WWDG_CR_T4   ((uint8_t)0x10)
 
#define WWDG_CR_T5   ((uint8_t)0x20)
 
#define WWDG_CR_T6   ((uint8_t)0x40)
 
#define WWDG_CR_WDGA   ((uint8_t)0x80)
 
#define WWDG_CFR_W   ((uint16_t)0x007F)
 
#define WWDG_CFR_W0   ((uint16_t)0x0001)
 
#define WWDG_CFR_W1   ((uint16_t)0x0002)
 
#define WWDG_CFR_W2   ((uint16_t)0x0004)
 
#define WWDG_CFR_W3   ((uint16_t)0x0008)
 
#define WWDG_CFR_W4   ((uint16_t)0x0010)
 
#define WWDG_CFR_W5   ((uint16_t)0x0020)
 
#define WWDG_CFR_W6   ((uint16_t)0x0040)
 
#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)
 
#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
 
#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
 
#define WWDG_CFR_EWI   ((uint16_t)0x0200)
 
#define WWDG_SR_EWIF   ((uint8_t)0x01)
 
#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)
 
#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)
 
#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)
 
#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)
 
#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)
 
#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)
 
#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)
 
#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040
 
#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080
 
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)
 
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)
 
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)
 
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)
 
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)
 
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)
 
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)
 
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)
 
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)
 
#define DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)
 
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)
 
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)
 
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
 
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
 
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
 
#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)
 
#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)
 
#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
#define DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)
 
#define DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)
 
#define DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)
 
#define DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)
 
#define DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)
 
#define ETH_MACCR_WD   ((uint32_t)0x00800000) /* Watchdog disable */
 
#define ETH_MACCR_JD   ((uint32_t)0x00400000) /* Jabber disable */
 
#define ETH_MACCR_IFG   ((uint32_t)0x000E0000) /* Inter-frame gap */
 
#define ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
 
#define ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
 
#define ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
 
#define ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
 
#define ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
 
#define ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
 
#define ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
 
#define ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
 
#define ETH_MACCR_CSD   ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
 
#define ETH_MACCR_FES   ((uint32_t)0x00004000) /* Fast ethernet speed */
 
#define ETH_MACCR_ROD   ((uint32_t)0x00002000) /* Receive own disable */
 
#define ETH_MACCR_LM   ((uint32_t)0x00001000) /* loopback mode */
 
#define ETH_MACCR_DM   ((uint32_t)0x00000800) /* Duplex mode */
 
#define ETH_MACCR_IPCO   ((uint32_t)0x00000400) /* IP Checksum offload */
 
#define ETH_MACCR_RD   ((uint32_t)0x00000200) /* Retry disable */
 
#define ETH_MACCR_APCS   ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
 
#define ETH_MACCR_BL
 
#define ETH_MACCR_BL_10   ((uint32_t)0x00000000) /* k = min (n, 10) */
 
#define ETH_MACCR_BL_8   ((uint32_t)0x00000020) /* k = min (n, 8) */
 
#define ETH_MACCR_BL_4   ((uint32_t)0x00000040) /* k = min (n, 4) */
 
#define ETH_MACCR_BL_1   ((uint32_t)0x00000060) /* k = min (n, 1) */
 
#define ETH_MACCR_DC   ((uint32_t)0x00000010) /* Defferal check */
 
#define ETH_MACCR_TE   ((uint32_t)0x00000008) /* Transmitter enable */
 
#define ETH_MACCR_RE   ((uint32_t)0x00000004) /* Receiver enable */
 
#define ETH_MACFFR_RA   ((uint32_t)0x80000000) /* Receive all */
 
#define ETH_MACFFR_HPF   ((uint32_t)0x00000400) /* Hash or perfect filter */
 
#define ETH_MACFFR_SAF   ((uint32_t)0x00000200) /* Source address filter enable */
 
#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100) /* SA inverse filtering */
 
#define ETH_MACFFR_PCF   ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
 
#define ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
 
#define ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
 
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
 
#define ETH_MACFFR_BFD   ((uint32_t)0x00000020) /* Broadcast frame disable */
 
#define ETH_MACFFR_PAM   ((uint32_t)0x00000010) /* Pass all mutlicast */
 
#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008) /* DA Inverse filtering */
 
#define ETH_MACFFR_HM   ((uint32_t)0x00000004) /* Hash multicast */
 
#define ETH_MACFFR_HU   ((uint32_t)0x00000002) /* Hash unicast */
 
#define ETH_MACFFR_PM   ((uint32_t)0x00000001) /* Promiscuous mode */
 
#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF) /* Hash table high */
 
#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF) /* Hash table low */
 
#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800) /* Physical layer address */
 
#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0) /* MII register in the selected PHY */
 
#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
 
#define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
 
#define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
 
#define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
 
#define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
 
#define ETH_MACMIIAR_CR_Div102   ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
 
#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002) /* MII write */
 
#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001) /* MII busy */
 
#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
 
#define ETH_MACFCR_PT   ((uint32_t)0xFFFF0000) /* Pause time */
 
#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080) /* Zero-quanta pause disable */
 
#define ETH_MACFCR_PLT   ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
 
#define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
 
#define ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
 
#define ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
 
#define ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
 
#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008) /* Unicast pause frame detect */
 
#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004) /* Receive flow control enable */
 
#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002) /* Transmit flow control enable */
 
#define ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
 
#define ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
 
#define ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
 
#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
 
#define ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
 
#define ETH_MACPMTCSR_GU   ((uint32_t)0x00000200) /* Global Unicast */
 
#define ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040) /* Wake-Up Frame Received */
 
#define ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020) /* Magic Packet Received */
 
#define ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
 
#define ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002) /* Magic Packet Enable */
 
#define ETH_MACPMTCSR_PD   ((uint32_t)0x00000001) /* Power Down */
 
#define ETH_MACSR_TSTS   ((uint32_t)0x00000200) /* Time stamp trigger status */
 
#define ETH_MACSR_MMCTS   ((uint32_t)0x00000040) /* MMC transmit status */
 
#define ETH_MACSR_MMMCRS   ((uint32_t)0x00000020) /* MMC receive status */
 
#define ETH_MACSR_MMCS   ((uint32_t)0x00000010) /* MMC status */
 
#define ETH_MACSR_PMTS   ((uint32_t)0x00000008) /* PMT status */
 
#define ETH_MACIMR_TSTIM   ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
 
#define ETH_MACIMR_PMTIM   ((uint32_t)0x00000008) /* PMT interrupt mask */
 
#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF) /* MAC address0 high */
 
#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
 
#define ETH_MACA1HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
#define ETH_MACA1HR_SA   ((uint32_t)0x40000000) /* Source address */
 
#define ETH_MACA1HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
 
#define ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
#define ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
#define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
#define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
#define ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
#define ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
 
#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF) /* MAC address1 high */
 
#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
 
#define ETH_MACA2HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
#define ETH_MACA2HR_SA   ((uint32_t)0x40000000) /* Source address */
 
#define ETH_MACA2HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */
 
#define ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
#define ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
#define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
#define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
#define ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
#define ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
 
#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF) /* MAC address1 high */
 
#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
 
#define ETH_MACA3HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
#define ETH_MACA3HR_SA   ((uint32_t)0x40000000) /* Source address */
 
#define ETH_MACA3HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */
 
#define ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
#define ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
#define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
#define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
#define ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
#define ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
 
#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF) /* MAC address3 high */
 
#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
 
#define ETH_MMCCR_MCFHP   ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
 
#define ETH_MMCCR_MCP   ((uint32_t)0x00000010) /* MMC counter preset */
 
#define ETH_MMCCR_MCF   ((uint32_t)0x00000008) /* MMC Counter Freeze */
 
#define ETH_MMCCR_ROR   ((uint32_t)0x00000004) /* Reset on Read */
 
#define ETH_MMCCR_CSR   ((uint32_t)0x00000002) /* Counter Stop Rollover */
 
#define ETH_MMCCR_CR   ((uint32_t)0x00000001) /* Counters Reset */
 
#define ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
 
#define ETH_MMCRIR_RFAES   ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
 
#define ETH_MMCRIR_RFCES   ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
 
#define ETH_MMCTIR_TGFS   ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
 
#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
 
#define ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
 
#define ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
 
#define ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
 
#define ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
#define ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
 
#define ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
 
#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
#define ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
#define ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
 
#define ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
 
#define ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
 
#define ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
 
#define ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000) /* Time stamp clock node type */
 
#define ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
 
#define ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
 
#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
 
#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
 
#define ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
 
#define ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
 
#define ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
 
#define ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
 
#define ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020) /* Addend register update */
 
#define ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
 
#define ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008) /* Time stamp update */
 
#define ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004) /* Time stamp initialize */
 
#define ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
 
#define ETH_PTPTSCR_TSE   ((uint32_t)0x00000001) /* Time stamp enable */
 
#define ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF) /* System time Sub-second increment value */
 
#define ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF) /* System Time second */
 
#define ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000) /* System Time Positive or negative time */
 
#define ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
 
#define ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
 
#define ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
 
#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
 
#define ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
 
#define ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
 
#define ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
 
#define ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020) /* Time stamp target time reached */
 
#define ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010) /* Time stamp seconds overflow */
 
#define ETH_DMABMR_AAB   ((uint32_t)0x02000000) /* Address-Aligned beats */
 
#define ETH_DMABMR_FPM   ((uint32_t)0x01000000) /* 4xPBL mode */
 
#define ETH_DMABMR_USP   ((uint32_t)0x00800000) /* Use separate PBL */
 
#define ETH_DMABMR_RDP   ((uint32_t)0x007E0000) /* RxDMA PBL */
 
#define ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
 
#define ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
 
#define ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
#define ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
#define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
#define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
#define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
#define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
#define ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
#define ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
#define ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
 
#define ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
 
#define ETH_DMABMR_FB   ((uint32_t)0x00010000) /* Fixed Burst */
 
#define ETH_DMABMR_RTPR   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000) /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000) /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000) /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
 
#define ETH_DMABMR_PBL   ((uint32_t)0x00003F00) /* Programmable burst length */
 
#define ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
 
#define ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
 
#define ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
#define ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
#define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
#define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
#define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
#define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
#define ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
#define ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
#define ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
 
#define ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
 
#define ETH_DMABMR_EDE   ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
 
#define ETH_DMABMR_DSL   ((uint32_t)0x0000007C) /* Descriptor Skip Length */
 
#define ETH_DMABMR_DA   ((uint32_t)0x00000002) /* DMA arbitration scheme */
 
#define ETH_DMABMR_SR   ((uint32_t)0x00000001) /* Software reset */
 
#define ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
 
#define ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
 
#define ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF) /* Start of receive list */
 
#define ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
 
#define ETH_DMASR_TSTS   ((uint32_t)0x20000000) /* Time-stamp trigger status */
 
#define ETH_DMASR_PMTS   ((uint32_t)0x10000000) /* PMT status */
 
#define ETH_DMASR_MMCS   ((uint32_t)0x08000000) /* MMC status */
 
#define ETH_DMASR_EBS   ((uint32_t)0x03800000) /* Error bits status */
 
#define ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
 
#define ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
 
#define ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
 
#define ETH_DMASR_TPS   ((uint32_t)0x00700000) /* Transmit process state */
 
#define ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
 
#define ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
 
#define ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000) /* Running - waiting for status */
 
#define ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000) /* Running - reading the data from host memory */
 
#define ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
 
#define ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
 
#define ETH_DMASR_RPS   ((uint32_t)0x000E0000) /* Receive process state */
 
#define ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
 
#define ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
 
#define ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000) /* Running - waiting for packet */
 
#define ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
 
#define ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000) /* Running - closing descriptor */
 
#define ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
 
#define ETH_DMASR_NIS   ((uint32_t)0x00010000) /* Normal interrupt summary */
 
#define ETH_DMASR_AIS   ((uint32_t)0x00008000) /* Abnormal interrupt summary */
 
#define ETH_DMASR_ERS   ((uint32_t)0x00004000) /* Early receive status */
 
#define ETH_DMASR_FBES   ((uint32_t)0x00002000) /* Fatal bus error status */
 
#define ETH_DMASR_ETS   ((uint32_t)0x00000400) /* Early transmit status */
 
#define ETH_DMASR_RWTS   ((uint32_t)0x00000200) /* Receive watchdog timeout status */
 
#define ETH_DMASR_RPSS   ((uint32_t)0x00000100) /* Receive process stopped status */
 
#define ETH_DMASR_RBUS   ((uint32_t)0x00000080) /* Receive buffer unavailable status */
 
#define ETH_DMASR_RS   ((uint32_t)0x00000040) /* Receive status */
 
#define ETH_DMASR_TUS   ((uint32_t)0x00000020) /* Transmit underflow status */
 
#define ETH_DMASR_ROS   ((uint32_t)0x00000010) /* Receive overflow status */
 
#define ETH_DMASR_TJTS   ((uint32_t)0x00000008) /* Transmit jabber timeout status */
 
#define ETH_DMASR_TBUS   ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
 
#define ETH_DMASR_TPSS   ((uint32_t)0x00000002) /* Transmit process stopped status */
 
#define ETH_DMASR_TS   ((uint32_t)0x00000001) /* Transmit status */
 
#define ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
 
#define ETH_DMAOMR_RSF   ((uint32_t)0x02000000) /* Receive store and forward */
 
#define ETH_DMAOMR_DFRF   ((uint32_t)0x01000000) /* Disable flushing of received frames */
 
#define ETH_DMAOMR_TSF   ((uint32_t)0x00200000) /* Transmit store and forward */
 
#define ETH_DMAOMR_FTF   ((uint32_t)0x00100000) /* Flush transmit FIFO */
 
#define ETH_DMAOMR_TTC   ((uint32_t)0x0001C000) /* Transmit threshold control */
 
#define ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
 
#define ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
 
#define ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
 
#define ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
 
#define ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
 
#define ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
 
#define ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
 
#define ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
 
#define ETH_DMAOMR_ST   ((uint32_t)0x00002000) /* Start/stop transmission command */
 
#define ETH_DMAOMR_FEF   ((uint32_t)0x00000080) /* Forward error frames */
 
#define ETH_DMAOMR_FUGF   ((uint32_t)0x00000040) /* Forward undersized good frames */
 
#define ETH_DMAOMR_RTC   ((uint32_t)0x00000018) /* receive threshold control */
 
#define ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
 
#define ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
 
#define ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
 
#define ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
 
#define ETH_DMAOMR_OSF   ((uint32_t)0x00000004) /* operate on second frame */
 
#define ETH_DMAOMR_SR   ((uint32_t)0x00000002) /* Start/stop receive */
 
#define ETH_DMAIER_NISE   ((uint32_t)0x00010000) /* Normal interrupt summary enable */
 
#define ETH_DMAIER_AISE   ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
 
#define ETH_DMAIER_ERIE   ((uint32_t)0x00004000) /* Early receive interrupt enable */
 
#define ETH_DMAIER_FBEIE   ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
 
#define ETH_DMAIER_ETIE   ((uint32_t)0x00000400) /* Early transmit interrupt enable */
 
#define ETH_DMAIER_RWTIE   ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
 
#define ETH_DMAIER_RPSIE   ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
 
#define ETH_DMAIER_RBUIE   ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
 
#define ETH_DMAIER_RIE   ((uint32_t)0x00000040) /* Receive interrupt enable */
 
#define ETH_DMAIER_TUIE   ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
 
#define ETH_DMAIER_ROIE   ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
 
#define ETH_DMAIER_TJTIE   ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
 
#define ETH_DMAIER_TBUIE   ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
 
#define ETH_DMAIER_TPSIE   ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
 
#define ETH_DMAIER_TIE   ((uint32_t)0x00000001) /* Transmit interrupt enable */
 
#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
 
#define ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
 
#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
 
#define ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
 
#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
 
#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
 
#define ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
 
#define ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
 

Detailed Description

Macro Definition Documentation

◆ ADC_CCR_ADCPRE

#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)

ADCPRE[1:0] bits (ADC prescaler)

◆ ADC_CCR_ADCPRE_0

#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)

Bit 0

◆ ADC_CCR_ADCPRE_1

#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)

Bit 1

◆ ADC_CCR_DDS

#define ADC_CCR_DDS   ((uint32_t)0x00002000)

DMA disable selection (Multi-ADC mode)

◆ ADC_CCR_DELAY

#define ADC_CCR_DELAY   ((uint32_t)0x00000F00)

DELAY[3:0] bits (Delay between 2 sampling phases)

◆ ADC_CCR_DELAY_0

#define ADC_CCR_DELAY_0   ((uint32_t)0x00000100)

Bit 0

◆ ADC_CCR_DELAY_1

#define ADC_CCR_DELAY_1   ((uint32_t)0x00000200)

Bit 1

◆ ADC_CCR_DELAY_2

#define ADC_CCR_DELAY_2   ((uint32_t)0x00000400)

Bit 2

◆ ADC_CCR_DELAY_3

#define ADC_CCR_DELAY_3   ((uint32_t)0x00000800)

Bit 3

◆ ADC_CCR_DMA

#define ADC_CCR_DMA   ((uint32_t)0x0000C000)

DMA[1:0] bits (Direct Memory Access mode for multimode)

◆ ADC_CCR_DMA_0

#define ADC_CCR_DMA_0   ((uint32_t)0x00004000)

Bit 0

◆ ADC_CCR_DMA_1

#define ADC_CCR_DMA_1   ((uint32_t)0x00008000)

Bit 1

◆ ADC_CCR_MULTI

#define ADC_CCR_MULTI   ((uint32_t)0x0000001F)

MULTI[4:0] bits (Multi-ADC mode selection)

◆ ADC_CCR_MULTI_0

#define ADC_CCR_MULTI_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_CCR_MULTI_1

#define ADC_CCR_MULTI_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_CCR_MULTI_2

#define ADC_CCR_MULTI_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_CCR_MULTI_3

#define ADC_CCR_MULTI_3   ((uint32_t)0x00000008)

Bit 3

◆ ADC_CCR_MULTI_4

#define ADC_CCR_MULTI_4   ((uint32_t)0x00000010)

Bit 4

◆ ADC_CCR_TSVREFE

#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

◆ ADC_CCR_VBATE

#define ADC_CCR_VBATE   ((uint32_t)0x00400000)

VBAT Enable

◆ ADC_CDR_DATA1

#define ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)

1st data of a pair of regular conversions

◆ ADC_CDR_DATA2

#define ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)

2nd data of a pair of regular conversions

◆ ADC_CR1_AWDCH

#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

◆ ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)

Bit 3

◆ ADC_CR1_AWDCH_4

#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)

Bit 4

◆ ADC_CR1_AWDEN

#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

◆ ADC_CR1_AWDIE

#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)

AAnalog Watchdog interrupt enable

◆ ADC_CR1_AWDSGL

#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

◆ ADC_CR1_DISCEN

#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)

Discontinuous mode on regular channels

◆ ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

◆ ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)

Bit 0

◆ ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)

Bit 1

◆ ADC_CR1_DISCNUM_2

#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)

Bit 2

◆ ADC_CR1_EOCIE

#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)

Interrupt enable for EOC

◆ ADC_CR1_JAUTO

#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)

Automatic injected group conversion

◆ ADC_CR1_JAWDEN

#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

◆ ADC_CR1_JDISCEN

#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)

Discontinuous mode on injected channels

◆ ADC_CR1_JEOCIE

#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)

Interrupt enable for injected channels

◆ ADC_CR1_OVRIE

#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)

overrun interrupt enable

◆ ADC_CR1_RES

#define ADC_CR1_RES   ((uint32_t)0x03000000)

RES[2:0] bits (Resolution)

◆ ADC_CR1_RES_0

#define ADC_CR1_RES_0   ((uint32_t)0x01000000)

Bit 0

◆ ADC_CR1_RES_1

#define ADC_CR1_RES_1   ((uint32_t)0x02000000)

Bit 1

◆ ADC_CR1_SCAN

#define ADC_CR1_SCAN   ((uint32_t)0x00000100)

Scan mode

◆ ADC_CR2_ADON

#define ADC_CR2_ADON   ((uint32_t)0x00000001)

A/D Converter ON / OFF

◆ ADC_CR2_ALIGN

#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)

Data Alignment

◆ ADC_CR2_CONT

#define ADC_CR2_CONT   ((uint32_t)0x00000002)

Continuous Conversion

◆ ADC_CR2_DDS

#define ADC_CR2_DDS   ((uint32_t)0x00000200)

DMA disable selection (Single ADC)

◆ ADC_CR2_DMA

#define ADC_CR2_DMA   ((uint32_t)0x00000100)

Direct Memory access mode

◆ ADC_CR2_EOCS

#define ADC_CR2_EOCS   ((uint32_t)0x00000400)

End of conversion selection

◆ ADC_CR2_EXTEN

#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)

EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)

◆ ADC_CR2_EXTEN_0

#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)

Bit 0

◆ ADC_CR2_EXTEN_1

#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)

Bit 1

◆ ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)

EXTSEL[3:0] bits (External Event Select for regular group)

◆ ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)

Bit 0

◆ ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)

Bit 1

◆ ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)

Bit 2

◆ ADC_CR2_EXTSEL_3

#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)

Bit 3

◆ ADC_CR2_JEXTEN

#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)

◆ ADC_CR2_JEXTEN_0

#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)

Bit 0

◆ ADC_CR2_JEXTEN_1

#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)

Bit 1

◆ ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)

JEXTSEL[3:0] bits (External event select for injected group)

◆ ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)

Bit 0

◆ ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)

Bit 1

◆ ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)

Bit 2

◆ ADC_CR2_JEXTSEL_3

#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)

Bit 3

◆ ADC_CR2_JSWSTART

#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)

Start Conversion of injected channels

◆ ADC_CR2_SWSTART

#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)

Start Conversion of regular channels

◆ ADC_CSR_AWD1

#define ADC_CSR_AWD1   ((uint32_t)0x00000001)

ADC1 Analog watchdog flag

◆ ADC_CSR_AWD2

#define ADC_CSR_AWD2   ((uint32_t)0x00000100)

ADC2 Analog watchdog flag

◆ ADC_CSR_AWD3

#define ADC_CSR_AWD3   ((uint32_t)0x00010000)

ADC3 Analog watchdog flag

◆ ADC_CSR_DOVR1

#define ADC_CSR_DOVR1   ((uint32_t)0x00000020)

ADC1 DMA overrun flag

◆ ADC_CSR_DOVR2

#define ADC_CSR_DOVR2   ((uint32_t)0x00002000)

ADC2 DMA overrun flag

◆ ADC_CSR_DOVR3

#define ADC_CSR_DOVR3   ((uint32_t)0x00200000)

ADC3 DMA overrun flag

◆ ADC_CSR_EOC1

#define ADC_CSR_EOC1   ((uint32_t)0x00000002)

ADC1 End of conversion

◆ ADC_CSR_EOC2

#define ADC_CSR_EOC2   ((uint32_t)0x00000200)

ADC2 End of conversion

◆ ADC_CSR_EOC3

#define ADC_CSR_EOC3   ((uint32_t)0x00020000)

ADC3 End of conversion

◆ ADC_CSR_JEOC1

#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)

ADC1 Injected channel end of conversion

◆ ADC_CSR_JEOC2

#define ADC_CSR_JEOC2   ((uint32_t)0x00000400)

ADC2 Injected channel end of conversion

◆ ADC_CSR_JEOC3

#define ADC_CSR_JEOC3   ((uint32_t)0x00040000)

ADC3 Injected channel end of conversion

◆ ADC_CSR_JSTRT1

#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)

ADC1 Injected channel Start flag

◆ ADC_CSR_JSTRT2

#define ADC_CSR_JSTRT2   ((uint32_t)0x00000800)

ADC2 Injected channel Start flag

◆ ADC_CSR_JSTRT3

#define ADC_CSR_JSTRT3   ((uint32_t)0x00080000)

ADC3 Injected channel Start flag

◆ ADC_CSR_STRT1

#define ADC_CSR_STRT1   ((uint32_t)0x00000010)

ADC1 Regular channel Start flag

◆ ADC_CSR_STRT2

#define ADC_CSR_STRT2   ((uint32_t)0x00001000)

ADC2 Regular channel Start flag

◆ ADC_CSR_STRT3

#define ADC_CSR_STRT3   ((uint32_t)0x00100000)

ADC3 Regular channel Start flag

◆ ADC_DR_ADC2DATA

#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)

ADC2 data

◆ ADC_DR_DATA

#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)

Regular data

◆ ADC_HTR_HT

#define ADC_HTR_HT   ((uint16_t)0x0FFF)

Analog watchdog high threshold

◆ ADC_JDR1_JDATA

#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)

Injected data

◆ ADC_JDR2_JDATA

#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)

Injected data

◆ ADC_JDR3_JDATA

#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)

Injected data

◆ ADC_JDR4_JDATA

#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)

Injected data

◆ ADC_JOFR1_JOFFSET1

#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)

Data offset for injected channel 1

◆ ADC_JOFR2_JOFFSET2

#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)

Data offset for injected channel 2

◆ ADC_JOFR3_JOFFSET3

#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)

Data offset for injected channel 3

◆ ADC_JOFR4_JOFFSET4

#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)

Data offset for injected channel 4

◆ ADC_JSQR_JL

#define ADC_JSQR_JL   ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

◆ ADC_JSQR_JL_0

#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)

Bit 0

◆ ADC_JSQR_JL_1

#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)

Bit 1

◆ ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

◆ ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)

Bit 3

◆ ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)

Bit 4

◆ ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

◆ ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)

Bit 0

◆ ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)

Bit 1

◆ ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)

Bit 2

◆ ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)

Bit 3

◆ ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)

Bit 4

◆ ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

◆ ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)

Bit 0

◆ ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)

Bit 1

◆ ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)

Bit 2

◆ ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)

Bit 3

◆ ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)

Bit 4

◆ ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

◆ ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)

Bit 0

◆ ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)

Bit 1

◆ ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)

Bit 2

◆ ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)

Bit 3

◆ ADC_JSQR_JSQ4_4

#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)

Bit 4

◆ ADC_LTR_LT

#define ADC_LTR_LT   ((uint16_t)0x0FFF)

Analog watchdog low threshold

◆ ADC_SMPR1_SMP10

#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

◆ ADC_SMPR1_SMP10_0

#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_SMPR1_SMP10_1

#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_SMPR1_SMP10_2

#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_SMPR1_SMP11

#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

◆ ADC_SMPR1_SMP11_0

#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)

Bit 0

◆ ADC_SMPR1_SMP11_1

#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)

Bit 1

◆ ADC_SMPR1_SMP11_2

#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)

Bit 2

◆ ADC_SMPR1_SMP12

#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

◆ ADC_SMPR1_SMP12_0

#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)

Bit 0

◆ ADC_SMPR1_SMP12_1

#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)

Bit 1

◆ ADC_SMPR1_SMP12_2

#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)

Bit 2

◆ ADC_SMPR1_SMP13

#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

◆ ADC_SMPR1_SMP13_0

#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)

Bit 0

◆ ADC_SMPR1_SMP13_1

#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)

Bit 1

◆ ADC_SMPR1_SMP13_2

#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)

Bit 2

◆ ADC_SMPR1_SMP14

#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

◆ ADC_SMPR1_SMP14_0

#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)

Bit 0

◆ ADC_SMPR1_SMP14_1

#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)

Bit 1

◆ ADC_SMPR1_SMP14_2

#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)

Bit 2

◆ ADC_SMPR1_SMP15

#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 15 Sample time selection)

◆ ADC_SMPR1_SMP15_0

#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)

Bit 0

◆ ADC_SMPR1_SMP15_1

#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)

Bit 1

◆ ADC_SMPR1_SMP15_2

#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)

Bit 2

◆ ADC_SMPR1_SMP16

#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

◆ ADC_SMPR1_SMP16_0

#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)

Bit 0

◆ ADC_SMPR1_SMP16_1

#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)

Bit 1

◆ ADC_SMPR1_SMP16_2

#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)

Bit 2

◆ ADC_SMPR1_SMP17

#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

◆ ADC_SMPR1_SMP17_0

#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)

Bit 0

◆ ADC_SMPR1_SMP17_1

#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)

Bit 1

◆ ADC_SMPR1_SMP17_2

#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)

Bit 2

◆ ADC_SMPR1_SMP18

#define ADC_SMPR1_SMP18   ((uint32_t)0x07000000)

SMP18[2:0] bits (Channel 18 Sample time selection)

◆ ADC_SMPR1_SMP18_0

#define ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)

Bit 0

◆ ADC_SMPR1_SMP18_1

#define ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)

Bit 1

◆ ADC_SMPR1_SMP18_2

#define ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)

Bit 2

◆ ADC_SMPR2_SMP0

#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

◆ ADC_SMPR2_SMP0_0

#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_SMPR2_SMP0_1

#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_SMPR2_SMP0_2

#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_SMPR2_SMP1

#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

◆ ADC_SMPR2_SMP1_0

#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)

Bit 0

◆ ADC_SMPR2_SMP1_1

#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)

Bit 1

◆ ADC_SMPR2_SMP1_2

#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)

Bit 2

◆ ADC_SMPR2_SMP2

#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

◆ ADC_SMPR2_SMP2_0

#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)

Bit 0

◆ ADC_SMPR2_SMP2_1

#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)

Bit 1

◆ ADC_SMPR2_SMP2_2

#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)

Bit 2

◆ ADC_SMPR2_SMP3

#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

◆ ADC_SMPR2_SMP3_0

#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)

Bit 0

◆ ADC_SMPR2_SMP3_1

#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)

Bit 1

◆ ADC_SMPR2_SMP3_2

#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)

Bit 2

◆ ADC_SMPR2_SMP4

#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

◆ ADC_SMPR2_SMP4_0

#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)

Bit 0

◆ ADC_SMPR2_SMP4_1

#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)

Bit 1

◆ ADC_SMPR2_SMP4_2

#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)

Bit 2

◆ ADC_SMPR2_SMP5

#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

◆ ADC_SMPR2_SMP5_0

#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)

Bit 0

◆ ADC_SMPR2_SMP5_1

#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)

Bit 1

◆ ADC_SMPR2_SMP5_2

#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)

Bit 2

◆ ADC_SMPR2_SMP6

#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

◆ ADC_SMPR2_SMP6_0

#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)

Bit 0

◆ ADC_SMPR2_SMP6_1

#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)

Bit 1

◆ ADC_SMPR2_SMP6_2

#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)

Bit 2

◆ ADC_SMPR2_SMP7

#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

◆ ADC_SMPR2_SMP7_0

#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)

Bit 0

◆ ADC_SMPR2_SMP7_1

#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)

Bit 1

◆ ADC_SMPR2_SMP7_2

#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)

Bit 2

◆ ADC_SMPR2_SMP8

#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

◆ ADC_SMPR2_SMP8_0

#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)

Bit 0

◆ ADC_SMPR2_SMP8_1

#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)

Bit 1

◆ ADC_SMPR2_SMP8_2

#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)

Bit 2

◆ ADC_SMPR2_SMP9

#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

◆ ADC_SMPR2_SMP9_0

#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)

Bit 0

◆ ADC_SMPR2_SMP9_1

#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)

Bit 1

◆ ADC_SMPR2_SMP9_2

#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)

Bit 2

◆ ADC_SQR1_L

#define ADC_SQR1_L   ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

◆ ADC_SQR1_L_0

#define ADC_SQR1_L_0   ((uint32_t)0x00100000)

Bit 0

◆ ADC_SQR1_L_1

#define ADC_SQR1_L_1   ((uint32_t)0x00200000)

Bit 1

◆ ADC_SQR1_L_2

#define ADC_SQR1_L_2   ((uint32_t)0x00400000)

Bit 2

◆ ADC_SQR1_L_3

#define ADC_SQR1_L_3   ((uint32_t)0x00800000)

Bit 3

◆ ADC_SQR1_SQ13

#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

◆ ADC_SQR1_SQ13_0

#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_SQR1_SQ13_1

#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_SQR1_SQ13_2

#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_SQR1_SQ13_3

#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)

Bit 3

◆ ADC_SQR1_SQ13_4

#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)

Bit 4

◆ ADC_SQR1_SQ14

#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

◆ ADC_SQR1_SQ14_0

#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)

Bit 0

◆ ADC_SQR1_SQ14_1

#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)

Bit 1

◆ ADC_SQR1_SQ14_2

#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)

Bit 2

◆ ADC_SQR1_SQ14_3

#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)

Bit 3

◆ ADC_SQR1_SQ14_4

#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)

Bit 4

◆ ADC_SQR1_SQ15

#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

◆ ADC_SQR1_SQ15_0

#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)

Bit 0

◆ ADC_SQR1_SQ15_1

#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)

Bit 1

◆ ADC_SQR1_SQ15_2

#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)

Bit 2

◆ ADC_SQR1_SQ15_3

#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)

Bit 3

◆ ADC_SQR1_SQ15_4

#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)

Bit 4

◆ ADC_SQR1_SQ16

#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

◆ ADC_SQR1_SQ16_0

#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)

Bit 0

◆ ADC_SQR1_SQ16_1

#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)

Bit 1

◆ ADC_SQR1_SQ16_2

#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)

Bit 2

◆ ADC_SQR1_SQ16_3

#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)

Bit 3

◆ ADC_SQR1_SQ16_4

#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)

Bit 4

◆ ADC_SQR2_SQ10

#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

◆ ADC_SQR2_SQ10_0

#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)

Bit 0

◆ ADC_SQR2_SQ10_1

#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)

Bit 1

◆ ADC_SQR2_SQ10_2

#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)

Bit 2

◆ ADC_SQR2_SQ10_3

#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)

Bit 3

◆ ADC_SQR2_SQ10_4

#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)

Bit 4

◆ ADC_SQR2_SQ11

#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

◆ ADC_SQR2_SQ11_0

#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)

Bit 0

◆ ADC_SQR2_SQ11_1

#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)

Bit 1

◆ ADC_SQR2_SQ11_2

#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)

Bit 2

◆ ADC_SQR2_SQ11_3

#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)

Bit 3

◆ ADC_SQR2_SQ11_4

#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)

Bit 4

◆ ADC_SQR2_SQ12

#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

◆ ADC_SQR2_SQ12_0

#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)

Bit 0

◆ ADC_SQR2_SQ12_1

#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)

Bit 1

◆ ADC_SQR2_SQ12_2

#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)

Bit 2

◆ ADC_SQR2_SQ12_3

#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)

Bit 3

◆ ADC_SQR2_SQ12_4

#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)

Bit 4

◆ ADC_SQR2_SQ7

#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

◆ ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)

Bit 3

◆ ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)

Bit 4

◆ ADC_SQR2_SQ8

#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

◆ ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)

Bit 0

◆ ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)

Bit 1

◆ ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)

Bit 2

◆ ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)

Bit 3

◆ ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)

Bit 4

◆ ADC_SQR2_SQ9

#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

◆ ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)

Bit 0

◆ ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)

Bit 1

◆ ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)

Bit 2

◆ ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)

Bit 3

◆ ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)

Bit 4

◆ ADC_SQR3_SQ1

#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

◆ ADC_SQR3_SQ1_0

#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)

Bit 0

◆ ADC_SQR3_SQ1_1

#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)

Bit 1

◆ ADC_SQR3_SQ1_2

#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)

Bit 2

◆ ADC_SQR3_SQ1_3

#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)

Bit 3

◆ ADC_SQR3_SQ1_4

#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)

Bit 4

◆ ADC_SQR3_SQ2

#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

◆ ADC_SQR3_SQ2_0

#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)

Bit 0

◆ ADC_SQR3_SQ2_1

#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)

Bit 1

◆ ADC_SQR3_SQ2_2

#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)

Bit 2

◆ ADC_SQR3_SQ2_3

#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)

Bit 3

◆ ADC_SQR3_SQ2_4

#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)

Bit 4

◆ ADC_SQR3_SQ3

#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

◆ ADC_SQR3_SQ3_0

#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)

Bit 0

◆ ADC_SQR3_SQ3_1

#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)

Bit 1

◆ ADC_SQR3_SQ3_2

#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)

Bit 2

◆ ADC_SQR3_SQ3_3

#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)

Bit 3

◆ ADC_SQR3_SQ3_4

#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)

Bit 4

◆ ADC_SQR3_SQ4

#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

◆ ADC_SQR3_SQ4_0

#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)

Bit 0

◆ ADC_SQR3_SQ4_1

#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)

Bit 1

◆ ADC_SQR3_SQ4_2

#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)

Bit 2

◆ ADC_SQR3_SQ4_3

#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)

Bit 3

◆ ADC_SQR3_SQ4_4

#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)

Bit 4

◆ ADC_SQR3_SQ5

#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

◆ ADC_SQR3_SQ5_0

#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)

Bit 0

◆ ADC_SQR3_SQ5_1

#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)

Bit 1

◆ ADC_SQR3_SQ5_2

#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)

Bit 2

◆ ADC_SQR3_SQ5_3

#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)

Bit 3

◆ ADC_SQR3_SQ5_4

#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)

Bit 4

◆ ADC_SQR3_SQ6

#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

◆ ADC_SQR3_SQ6_0

#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)

Bit 0

◆ ADC_SQR3_SQ6_1

#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)

Bit 1

◆ ADC_SQR3_SQ6_2

#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)

Bit 2

◆ ADC_SQR3_SQ6_3

#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)

Bit 3

◆ ADC_SQR3_SQ6_4

#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)

Bit 4

◆ ADC_SR_AWD

#define ADC_SR_AWD   ((uint8_t)0x01)

Analog watchdog flag

◆ ADC_SR_EOC

#define ADC_SR_EOC   ((uint8_t)0x02)

End of conversion

◆ ADC_SR_JEOC

#define ADC_SR_JEOC   ((uint8_t)0x04)

Injected channel end of conversion

◆ ADC_SR_JSTRT

#define ADC_SR_JSTRT   ((uint8_t)0x08)

Injected channel Start flag

◆ ADC_SR_OVR

#define ADC_SR_OVR   ((uint8_t)0x20)

Overrun flag

◆ ADC_SR_STRT

#define ADC_SR_STRT   ((uint8_t)0x10)

Regular channel Start flag

◆ CAN_BTR_BRP

#define CAN_BTR_BRP   ((uint32_t)0x000003FF)

Baud Rate Prescaler

◆ CAN_BTR_LBKM

#define CAN_BTR_LBKM   ((uint32_t)0x40000000)

Loop Back Mode (Debug)

◆ CAN_BTR_SILM

#define CAN_BTR_SILM   ((uint32_t)0x80000000)

Silent Mode Mailbox registers

◆ CAN_BTR_SJW

#define CAN_BTR_SJW   ((uint32_t)0x03000000)

Resynchronization Jump Width

◆ CAN_BTR_TS1

#define CAN_BTR_TS1   ((uint32_t)0x000F0000)

Time Segment 1

◆ CAN_BTR_TS2

#define CAN_BTR_TS2   ((uint32_t)0x00700000)

Time Segment 2

◆ CAN_ESR_BOFF

#define CAN_ESR_BOFF   ((uint32_t)0x00000004)

Bus-Off Flag

◆ CAN_ESR_EPVF

#define CAN_ESR_EPVF   ((uint32_t)0x00000002)

Error Passive Flag

◆ CAN_ESR_EWGF

#define CAN_ESR_EWGF   ((uint32_t)0x00000001)

Error Warning Flag

◆ CAN_ESR_LEC

#define CAN_ESR_LEC   ((uint32_t)0x00000070)

LEC[2:0] bits (Last Error Code)

◆ CAN_ESR_LEC_0

#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)

Bit 0

◆ CAN_ESR_LEC_1

#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)

Bit 1

◆ CAN_ESR_LEC_2

#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)

Bit 2

◆ CAN_ESR_REC

#define CAN_ESR_REC   ((uint32_t)0xFF000000)

Receive Error Counter

◆ CAN_ESR_TEC

#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)

Least significant byte of the 9-bit Transmit Error Counter

◆ CAN_F0R1_FB0

#define CAN_F0R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F0R1_FB1

#define CAN_F0R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F0R1_FB10

#define CAN_F0R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F0R1_FB11

#define CAN_F0R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F0R1_FB12

#define CAN_F0R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F0R1_FB13

#define CAN_F0R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F0R1_FB14

#define CAN_F0R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F0R1_FB15

#define CAN_F0R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F0R1_FB16

#define CAN_F0R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F0R1_FB17

#define CAN_F0R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F0R1_FB18

#define CAN_F0R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F0R1_FB19

#define CAN_F0R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F0R1_FB2

#define CAN_F0R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F0R1_FB20

#define CAN_F0R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F0R1_FB21

#define CAN_F0R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F0R1_FB22

#define CAN_F0R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F0R1_FB23

#define CAN_F0R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F0R1_FB24

#define CAN_F0R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F0R1_FB25

#define CAN_F0R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F0R1_FB26

#define CAN_F0R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F0R1_FB27

#define CAN_F0R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F0R1_FB28

#define CAN_F0R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F0R1_FB29

#define CAN_F0R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F0R1_FB3

#define CAN_F0R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F0R1_FB30

#define CAN_F0R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F0R1_FB31

#define CAN_F0R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F0R1_FB4

#define CAN_F0R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F0R1_FB5

#define CAN_F0R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F0R1_FB6

#define CAN_F0R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F0R1_FB7

#define CAN_F0R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F0R1_FB8

#define CAN_F0R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F0R1_FB9

#define CAN_F0R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F0R2_FB0

#define CAN_F0R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F0R2_FB1

#define CAN_F0R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F0R2_FB10

#define CAN_F0R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F0R2_FB11

#define CAN_F0R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F0R2_FB12

#define CAN_F0R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F0R2_FB13

#define CAN_F0R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F0R2_FB14

#define CAN_F0R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F0R2_FB15

#define CAN_F0R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F0R2_FB16

#define CAN_F0R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F0R2_FB17

#define CAN_F0R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F0R2_FB18

#define CAN_F0R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F0R2_FB19

#define CAN_F0R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F0R2_FB2

#define CAN_F0R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F0R2_FB20

#define CAN_F0R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F0R2_FB21

#define CAN_F0R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F0R2_FB22

#define CAN_F0R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F0R2_FB23

#define CAN_F0R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F0R2_FB24

#define CAN_F0R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F0R2_FB25

#define CAN_F0R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F0R2_FB26

#define CAN_F0R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F0R2_FB27

#define CAN_F0R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F0R2_FB28

#define CAN_F0R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F0R2_FB29

#define CAN_F0R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F0R2_FB3

#define CAN_F0R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F0R2_FB30

#define CAN_F0R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F0R2_FB31

#define CAN_F0R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F0R2_FB4

#define CAN_F0R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F0R2_FB5

#define CAN_F0R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F0R2_FB6

#define CAN_F0R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F0R2_FB7

#define CAN_F0R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F0R2_FB8

#define CAN_F0R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F0R2_FB9

#define CAN_F0R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F10R1_FB0

#define CAN_F10R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F10R1_FB1

#define CAN_F10R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F10R1_FB10

#define CAN_F10R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F10R1_FB11

#define CAN_F10R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F10R1_FB12

#define CAN_F10R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F10R1_FB13

#define CAN_F10R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F10R1_FB14

#define CAN_F10R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F10R1_FB15

#define CAN_F10R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F10R1_FB16

#define CAN_F10R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F10R1_FB17

#define CAN_F10R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F10R1_FB18

#define CAN_F10R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F10R1_FB19

#define CAN_F10R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F10R1_FB2

#define CAN_F10R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F10R1_FB20

#define CAN_F10R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F10R1_FB21

#define CAN_F10R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F10R1_FB22

#define CAN_F10R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F10R1_FB23

#define CAN_F10R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F10R1_FB24

#define CAN_F10R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F10R1_FB25

#define CAN_F10R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F10R1_FB26

#define CAN_F10R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F10R1_FB27

#define CAN_F10R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F10R1_FB28

#define CAN_F10R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F10R1_FB29

#define CAN_F10R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F10R1_FB3

#define CAN_F10R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F10R1_FB30

#define CAN_F10R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F10R1_FB31

#define CAN_F10R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F10R1_FB4

#define CAN_F10R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F10R1_FB5

#define CAN_F10R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F10R1_FB6

#define CAN_F10R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F10R1_FB7

#define CAN_F10R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F10R1_FB8

#define CAN_F10R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F10R1_FB9

#define CAN_F10R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F10R2_FB0

#define CAN_F10R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F10R2_FB1

#define CAN_F10R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F10R2_FB10

#define CAN_F10R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F10R2_FB11

#define CAN_F10R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F10R2_FB12

#define CAN_F10R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F10R2_FB13

#define CAN_F10R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F10R2_FB14

#define CAN_F10R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F10R2_FB15

#define CAN_F10R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F10R2_FB16

#define CAN_F10R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F10R2_FB17

#define CAN_F10R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F10R2_FB18

#define CAN_F10R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F10R2_FB19

#define CAN_F10R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F10R2_FB2

#define CAN_F10R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F10R2_FB20

#define CAN_F10R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F10R2_FB21

#define CAN_F10R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F10R2_FB22

#define CAN_F10R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F10R2_FB23

#define CAN_F10R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F10R2_FB24

#define CAN_F10R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F10R2_FB25

#define CAN_F10R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F10R2_FB26

#define CAN_F10R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F10R2_FB27

#define CAN_F10R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F10R2_FB28

#define CAN_F10R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F10R2_FB29

#define CAN_F10R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F10R2_FB3

#define CAN_F10R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F10R2_FB30

#define CAN_F10R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F10R2_FB31

#define CAN_F10R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F10R2_FB4

#define CAN_F10R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F10R2_FB5

#define CAN_F10R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F10R2_FB6

#define CAN_F10R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F10R2_FB7

#define CAN_F10R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F10R2_FB8

#define CAN_F10R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F10R2_FB9

#define CAN_F10R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F11R1_FB0

#define CAN_F11R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F11R1_FB1

#define CAN_F11R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F11R1_FB10

#define CAN_F11R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F11R1_FB11

#define CAN_F11R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F11R1_FB12

#define CAN_F11R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F11R1_FB13

#define CAN_F11R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F11R1_FB14

#define CAN_F11R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F11R1_FB15

#define CAN_F11R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F11R1_FB16

#define CAN_F11R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F11R1_FB17

#define CAN_F11R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F11R1_FB18

#define CAN_F11R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F11R1_FB19

#define CAN_F11R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F11R1_FB2

#define CAN_F11R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F11R1_FB20

#define CAN_F11R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F11R1_FB21

#define CAN_F11R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F11R1_FB22

#define CAN_F11R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F11R1_FB23

#define CAN_F11R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F11R1_FB24

#define CAN_F11R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F11R1_FB25

#define CAN_F11R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F11R1_FB26

#define CAN_F11R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F11R1_FB27

#define CAN_F11R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F11R1_FB28

#define CAN_F11R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F11R1_FB29

#define CAN_F11R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F11R1_FB3

#define CAN_F11R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F11R1_FB30

#define CAN_F11R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F11R1_FB31

#define CAN_F11R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F11R1_FB4

#define CAN_F11R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F11R1_FB5

#define CAN_F11R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F11R1_FB6

#define CAN_F11R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F11R1_FB7

#define CAN_F11R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F11R1_FB8

#define CAN_F11R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F11R1_FB9

#define CAN_F11R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F11R2_FB0

#define CAN_F11R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F11R2_FB1

#define CAN_F11R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F11R2_FB10

#define CAN_F11R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F11R2_FB11

#define CAN_F11R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F11R2_FB12

#define CAN_F11R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F11R2_FB13

#define CAN_F11R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F11R2_FB14

#define CAN_F11R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F11R2_FB15

#define CAN_F11R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F11R2_FB16

#define CAN_F11R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F11R2_FB17

#define CAN_F11R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F11R2_FB18

#define CAN_F11R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F11R2_FB19

#define CAN_F11R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F11R2_FB2

#define CAN_F11R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F11R2_FB20

#define CAN_F11R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F11R2_FB21

#define CAN_F11R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F11R2_FB22

#define CAN_F11R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F11R2_FB23

#define CAN_F11R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F11R2_FB24

#define CAN_F11R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F11R2_FB25

#define CAN_F11R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F11R2_FB26

#define CAN_F11R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F11R2_FB27

#define CAN_F11R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F11R2_FB28

#define CAN_F11R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F11R2_FB29

#define CAN_F11R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F11R2_FB3

#define CAN_F11R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F11R2_FB30

#define CAN_F11R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F11R2_FB31

#define CAN_F11R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F11R2_FB4

#define CAN_F11R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F11R2_FB5

#define CAN_F11R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F11R2_FB6

#define CAN_F11R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F11R2_FB7

#define CAN_F11R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F11R2_FB8

#define CAN_F11R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F11R2_FB9

#define CAN_F11R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F12R1_FB0

#define CAN_F12R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F12R1_FB1

#define CAN_F12R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F12R1_FB10

#define CAN_F12R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F12R1_FB11

#define CAN_F12R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F12R1_FB12

#define CAN_F12R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F12R1_FB13

#define CAN_F12R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F12R1_FB14

#define CAN_F12R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F12R1_FB15

#define CAN_F12R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F12R1_FB16

#define CAN_F12R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F12R1_FB17

#define CAN_F12R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F12R1_FB18

#define CAN_F12R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F12R1_FB19

#define CAN_F12R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F12R1_FB2

#define CAN_F12R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F12R1_FB20

#define CAN_F12R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F12R1_FB21

#define CAN_F12R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F12R1_FB22

#define CAN_F12R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F12R1_FB23

#define CAN_F12R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F12R1_FB24

#define CAN_F12R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F12R1_FB25

#define CAN_F12R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F12R1_FB26

#define CAN_F12R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F12R1_FB27

#define CAN_F12R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F12R1_FB28

#define CAN_F12R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F12R1_FB29

#define CAN_F12R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F12R1_FB3

#define CAN_F12R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F12R1_FB30

#define CAN_F12R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F12R1_FB31

#define CAN_F12R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F12R1_FB4

#define CAN_F12R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F12R1_FB5

#define CAN_F12R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F12R1_FB6

#define CAN_F12R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F12R1_FB7

#define CAN_F12R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F12R1_FB8

#define CAN_F12R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F12R1_FB9

#define CAN_F12R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F12R2_FB0

#define CAN_F12R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F12R2_FB1

#define CAN_F12R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F12R2_FB10

#define CAN_F12R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F12R2_FB11

#define CAN_F12R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F12R2_FB12

#define CAN_F12R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F12R2_FB13

#define CAN_F12R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F12R2_FB14

#define CAN_F12R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F12R2_FB15

#define CAN_F12R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F12R2_FB16

#define CAN_F12R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F12R2_FB17

#define CAN_F12R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F12R2_FB18

#define CAN_F12R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F12R2_FB19

#define CAN_F12R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F12R2_FB2

#define CAN_F12R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F12R2_FB20

#define CAN_F12R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F12R2_FB21

#define CAN_F12R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F12R2_FB22

#define CAN_F12R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F12R2_FB23

#define CAN_F12R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F12R2_FB24

#define CAN_F12R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F12R2_FB25

#define CAN_F12R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F12R2_FB26

#define CAN_F12R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F12R2_FB27

#define CAN_F12R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F12R2_FB28

#define CAN_F12R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F12R2_FB29

#define CAN_F12R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F12R2_FB3

#define CAN_F12R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F12R2_FB30

#define CAN_F12R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F12R2_FB31

#define CAN_F12R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F12R2_FB4

#define CAN_F12R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F12R2_FB5

#define CAN_F12R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F12R2_FB6

#define CAN_F12R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F12R2_FB7

#define CAN_F12R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F12R2_FB8

#define CAN_F12R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F12R2_FB9

#define CAN_F12R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F13R1_FB0

#define CAN_F13R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F13R1_FB1

#define CAN_F13R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F13R1_FB10

#define CAN_F13R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F13R1_FB11

#define CAN_F13R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F13R1_FB12

#define CAN_F13R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F13R1_FB13

#define CAN_F13R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F13R1_FB14

#define CAN_F13R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F13R1_FB15

#define CAN_F13R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F13R1_FB16

#define CAN_F13R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F13R1_FB17

#define CAN_F13R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F13R1_FB18

#define CAN_F13R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F13R1_FB19

#define CAN_F13R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F13R1_FB2

#define CAN_F13R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F13R1_FB20

#define CAN_F13R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F13R1_FB21

#define CAN_F13R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F13R1_FB22

#define CAN_F13R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F13R1_FB23

#define CAN_F13R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F13R1_FB24

#define CAN_F13R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F13R1_FB25

#define CAN_F13R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F13R1_FB26

#define CAN_F13R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F13R1_FB27

#define CAN_F13R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F13R1_FB28

#define CAN_F13R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F13R1_FB29

#define CAN_F13R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F13R1_FB3

#define CAN_F13R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F13R1_FB30

#define CAN_F13R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F13R1_FB31

#define CAN_F13R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F13R1_FB4

#define CAN_F13R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F13R1_FB5

#define CAN_F13R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F13R1_FB6

#define CAN_F13R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F13R1_FB7

#define CAN_F13R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F13R1_FB8

#define CAN_F13R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F13R1_FB9

#define CAN_F13R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F13R2_FB0

#define CAN_F13R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F13R2_FB1

#define CAN_F13R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F13R2_FB10

#define CAN_F13R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F13R2_FB11

#define CAN_F13R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F13R2_FB12

#define CAN_F13R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F13R2_FB13

#define CAN_F13R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F13R2_FB14

#define CAN_F13R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F13R2_FB15

#define CAN_F13R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F13R2_FB16

#define CAN_F13R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F13R2_FB17

#define CAN_F13R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F13R2_FB18

#define CAN_F13R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F13R2_FB19

#define CAN_F13R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F13R2_FB2

#define CAN_F13R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F13R2_FB20

#define CAN_F13R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F13R2_FB21

#define CAN_F13R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F13R2_FB22

#define CAN_F13R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F13R2_FB23

#define CAN_F13R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F13R2_FB24

#define CAN_F13R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F13R2_FB25

#define CAN_F13R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F13R2_FB26

#define CAN_F13R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F13R2_FB27

#define CAN_F13R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F13R2_FB28

#define CAN_F13R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F13R2_FB29

#define CAN_F13R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F13R2_FB3

#define CAN_F13R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F13R2_FB30

#define CAN_F13R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F13R2_FB31

#define CAN_F13R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F13R2_FB4

#define CAN_F13R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F13R2_FB5

#define CAN_F13R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F13R2_FB6

#define CAN_F13R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F13R2_FB7

#define CAN_F13R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F13R2_FB8

#define CAN_F13R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F13R2_FB9

#define CAN_F13R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F1R1_FB0

#define CAN_F1R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F1R1_FB1

#define CAN_F1R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F1R1_FB10

#define CAN_F1R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F1R1_FB11

#define CAN_F1R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F1R1_FB12

#define CAN_F1R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F1R1_FB13

#define CAN_F1R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F1R1_FB14

#define CAN_F1R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F1R1_FB15

#define CAN_F1R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F1R1_FB16

#define CAN_F1R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F1R1_FB17

#define CAN_F1R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F1R1_FB18

#define CAN_F1R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F1R1_FB19

#define CAN_F1R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F1R1_FB2

#define CAN_F1R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F1R1_FB20

#define CAN_F1R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F1R1_FB21

#define CAN_F1R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F1R1_FB22

#define CAN_F1R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F1R1_FB23

#define CAN_F1R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F1R1_FB24

#define CAN_F1R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F1R1_FB25

#define CAN_F1R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F1R1_FB26

#define CAN_F1R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F1R1_FB27

#define CAN_F1R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F1R1_FB28

#define CAN_F1R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F1R1_FB29

#define CAN_F1R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F1R1_FB3

#define CAN_F1R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F1R1_FB30

#define CAN_F1R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F1R1_FB31

#define CAN_F1R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F1R1_FB4

#define CAN_F1R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F1R1_FB5

#define CAN_F1R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F1R1_FB6

#define CAN_F1R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F1R1_FB7

#define CAN_F1R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F1R1_FB8

#define CAN_F1R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F1R1_FB9

#define CAN_F1R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F1R2_FB0

#define CAN_F1R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F1R2_FB1

#define CAN_F1R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F1R2_FB10

#define CAN_F1R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F1R2_FB11

#define CAN_F1R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F1R2_FB12

#define CAN_F1R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F1R2_FB13

#define CAN_F1R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F1R2_FB14

#define CAN_F1R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F1R2_FB15

#define CAN_F1R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F1R2_FB16

#define CAN_F1R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F1R2_FB17

#define CAN_F1R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F1R2_FB18

#define CAN_F1R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F1R2_FB19

#define CAN_F1R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F1R2_FB2

#define CAN_F1R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F1R2_FB20

#define CAN_F1R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F1R2_FB21

#define CAN_F1R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F1R2_FB22

#define CAN_F1R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F1R2_FB23

#define CAN_F1R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F1R2_FB24

#define CAN_F1R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F1R2_FB25

#define CAN_F1R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F1R2_FB26

#define CAN_F1R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F1R2_FB27

#define CAN_F1R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F1R2_FB28

#define CAN_F1R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F1R2_FB29

#define CAN_F1R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F1R2_FB3

#define CAN_F1R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F1R2_FB30

#define CAN_F1R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F1R2_FB31

#define CAN_F1R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F1R2_FB4

#define CAN_F1R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F1R2_FB5

#define CAN_F1R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F1R2_FB6

#define CAN_F1R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F1R2_FB7

#define CAN_F1R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F1R2_FB8

#define CAN_F1R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F1R2_FB9

#define CAN_F1R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F2R1_FB0

#define CAN_F2R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F2R1_FB1

#define CAN_F2R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F2R1_FB10

#define CAN_F2R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F2R1_FB11

#define CAN_F2R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F2R1_FB12

#define CAN_F2R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F2R1_FB13

#define CAN_F2R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F2R1_FB14

#define CAN_F2R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F2R1_FB15

#define CAN_F2R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F2R1_FB16

#define CAN_F2R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F2R1_FB17

#define CAN_F2R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F2R1_FB18

#define CAN_F2R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F2R1_FB19

#define CAN_F2R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F2R1_FB2

#define CAN_F2R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F2R1_FB20

#define CAN_F2R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F2R1_FB21

#define CAN_F2R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F2R1_FB22

#define CAN_F2R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F2R1_FB23

#define CAN_F2R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F2R1_FB24

#define CAN_F2R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F2R1_FB25

#define CAN_F2R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F2R1_FB26

#define CAN_F2R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F2R1_FB27

#define CAN_F2R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F2R1_FB28

#define CAN_F2R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F2R1_FB29

#define CAN_F2R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F2R1_FB3

#define CAN_F2R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F2R1_FB30

#define CAN_F2R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F2R1_FB31

#define CAN_F2R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F2R1_FB4

#define CAN_F2R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F2R1_FB5

#define CAN_F2R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F2R1_FB6

#define CAN_F2R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F2R1_FB7

#define CAN_F2R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F2R1_FB8

#define CAN_F2R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F2R1_FB9

#define CAN_F2R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F2R2_FB0

#define CAN_F2R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F2R2_FB1

#define CAN_F2R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F2R2_FB10

#define CAN_F2R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F2R2_FB11

#define CAN_F2R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F2R2_FB12

#define CAN_F2R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F2R2_FB13

#define CAN_F2R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F2R2_FB14

#define CAN_F2R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F2R2_FB15

#define CAN_F2R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F2R2_FB16

#define CAN_F2R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F2R2_FB17

#define CAN_F2R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F2R2_FB18

#define CAN_F2R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F2R2_FB19

#define CAN_F2R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F2R2_FB2

#define CAN_F2R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F2R2_FB20

#define CAN_F2R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F2R2_FB21

#define CAN_F2R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F2R2_FB22

#define CAN_F2R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F2R2_FB23

#define CAN_F2R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F2R2_FB24

#define CAN_F2R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F2R2_FB25

#define CAN_F2R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F2R2_FB26

#define CAN_F2R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F2R2_FB27

#define CAN_F2R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F2R2_FB28

#define CAN_F2R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F2R2_FB29

#define CAN_F2R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F2R2_FB3

#define CAN_F2R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F2R2_FB30

#define CAN_F2R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F2R2_FB31

#define CAN_F2R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F2R2_FB4

#define CAN_F2R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F2R2_FB5

#define CAN_F2R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F2R2_FB6

#define CAN_F2R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F2R2_FB7

#define CAN_F2R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F2R2_FB8

#define CAN_F2R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F2R2_FB9

#define CAN_F2R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F3R1_FB0

#define CAN_F3R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F3R1_FB1

#define CAN_F3R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F3R1_FB10

#define CAN_F3R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F3R1_FB11

#define CAN_F3R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F3R1_FB12

#define CAN_F3R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F3R1_FB13

#define CAN_F3R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F3R1_FB14

#define CAN_F3R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F3R1_FB15

#define CAN_F3R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F3R1_FB16

#define CAN_F3R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F3R1_FB17

#define CAN_F3R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F3R1_FB18

#define CAN_F3R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F3R1_FB19

#define CAN_F3R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F3R1_FB2

#define CAN_F3R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F3R1_FB20

#define CAN_F3R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F3R1_FB21

#define CAN_F3R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F3R1_FB22

#define CAN_F3R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F3R1_FB23

#define CAN_F3R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F3R1_FB24

#define CAN_F3R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F3R1_FB25

#define CAN_F3R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F3R1_FB26

#define CAN_F3R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F3R1_FB27

#define CAN_F3R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F3R1_FB28

#define CAN_F3R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F3R1_FB29

#define CAN_F3R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F3R1_FB3

#define CAN_F3R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F3R1_FB30

#define CAN_F3R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F3R1_FB31

#define CAN_F3R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F3R1_FB4

#define CAN_F3R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F3R1_FB5

#define CAN_F3R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F3R1_FB6

#define CAN_F3R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F3R1_FB7

#define CAN_F3R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F3R1_FB8

#define CAN_F3R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F3R1_FB9

#define CAN_F3R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F3R2_FB0

#define CAN_F3R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F3R2_FB1

#define CAN_F3R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F3R2_FB10

#define CAN_F3R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F3R2_FB11

#define CAN_F3R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F3R2_FB12

#define CAN_F3R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F3R2_FB13

#define CAN_F3R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F3R2_FB14

#define CAN_F3R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F3R2_FB15

#define CAN_F3R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F3R2_FB16

#define CAN_F3R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F3R2_FB17

#define CAN_F3R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F3R2_FB18

#define CAN_F3R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F3R2_FB19

#define CAN_F3R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F3R2_FB2

#define CAN_F3R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F3R2_FB20

#define CAN_F3R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F3R2_FB21

#define CAN_F3R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F3R2_FB22

#define CAN_F3R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F3R2_FB23

#define CAN_F3R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F3R2_FB24

#define CAN_F3R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F3R2_FB25

#define CAN_F3R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F3R2_FB26

#define CAN_F3R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F3R2_FB27

#define CAN_F3R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F3R2_FB28

#define CAN_F3R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F3R2_FB29

#define CAN_F3R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F3R2_FB3

#define CAN_F3R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F3R2_FB30

#define CAN_F3R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F3R2_FB31

#define CAN_F3R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F3R2_FB4

#define CAN_F3R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F3R2_FB5

#define CAN_F3R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F3R2_FB6

#define CAN_F3R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F3R2_FB7

#define CAN_F3R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F3R2_FB8

#define CAN_F3R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F3R2_FB9

#define CAN_F3R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F4R1_FB0

#define CAN_F4R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F4R1_FB1

#define CAN_F4R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F4R1_FB10

#define CAN_F4R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F4R1_FB11

#define CAN_F4R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F4R1_FB12

#define CAN_F4R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F4R1_FB13

#define CAN_F4R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F4R1_FB14

#define CAN_F4R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F4R1_FB15

#define CAN_F4R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F4R1_FB16

#define CAN_F4R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F4R1_FB17

#define CAN_F4R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F4R1_FB18

#define CAN_F4R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F4R1_FB19

#define CAN_F4R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F4R1_FB2

#define CAN_F4R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F4R1_FB20

#define CAN_F4R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F4R1_FB21

#define CAN_F4R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F4R1_FB22

#define CAN_F4R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F4R1_FB23

#define CAN_F4R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F4R1_FB24

#define CAN_F4R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F4R1_FB25

#define CAN_F4R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F4R1_FB26

#define CAN_F4R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F4R1_FB27

#define CAN_F4R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F4R1_FB28

#define CAN_F4R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F4R1_FB29

#define CAN_F4R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F4R1_FB3

#define CAN_F4R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F4R1_FB30

#define CAN_F4R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F4R1_FB31

#define CAN_F4R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F4R1_FB4

#define CAN_F4R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F4R1_FB5

#define CAN_F4R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F4R1_FB6

#define CAN_F4R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F4R1_FB7

#define CAN_F4R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F4R1_FB8

#define CAN_F4R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F4R1_FB9

#define CAN_F4R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F4R2_FB0

#define CAN_F4R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F4R2_FB1

#define CAN_F4R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F4R2_FB10

#define CAN_F4R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F4R2_FB11

#define CAN_F4R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F4R2_FB12

#define CAN_F4R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F4R2_FB13

#define CAN_F4R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F4R2_FB14

#define CAN_F4R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F4R2_FB15

#define CAN_F4R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F4R2_FB16

#define CAN_F4R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F4R2_FB17

#define CAN_F4R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F4R2_FB18

#define CAN_F4R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F4R2_FB19

#define CAN_F4R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F4R2_FB2

#define CAN_F4R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F4R2_FB20

#define CAN_F4R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F4R2_FB21

#define CAN_F4R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F4R2_FB22

#define CAN_F4R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F4R2_FB23

#define CAN_F4R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F4R2_FB24

#define CAN_F4R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F4R2_FB25

#define CAN_F4R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F4R2_FB26

#define CAN_F4R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F4R2_FB27

#define CAN_F4R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F4R2_FB28

#define CAN_F4R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F4R2_FB29

#define CAN_F4R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F4R2_FB3

#define CAN_F4R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F4R2_FB30

#define CAN_F4R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F4R2_FB31

#define CAN_F4R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F4R2_FB4

#define CAN_F4R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F4R2_FB5

#define CAN_F4R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F4R2_FB6

#define CAN_F4R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F4R2_FB7

#define CAN_F4R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F4R2_FB8

#define CAN_F4R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F4R2_FB9

#define CAN_F4R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F5R1_FB0

#define CAN_F5R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F5R1_FB1

#define CAN_F5R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F5R1_FB10

#define CAN_F5R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F5R1_FB11

#define CAN_F5R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F5R1_FB12

#define CAN_F5R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F5R1_FB13

#define CAN_F5R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F5R1_FB14

#define CAN_F5R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F5R1_FB15

#define CAN_F5R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F5R1_FB16

#define CAN_F5R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F5R1_FB17

#define CAN_F5R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F5R1_FB18

#define CAN_F5R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F5R1_FB19

#define CAN_F5R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F5R1_FB2

#define CAN_F5R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F5R1_FB20

#define CAN_F5R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F5R1_FB21

#define CAN_F5R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F5R1_FB22

#define CAN_F5R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F5R1_FB23

#define CAN_F5R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F5R1_FB24

#define CAN_F5R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F5R1_FB25

#define CAN_F5R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F5R1_FB26

#define CAN_F5R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F5R1_FB27

#define CAN_F5R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F5R1_FB28

#define CAN_F5R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F5R1_FB29

#define CAN_F5R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F5R1_FB3

#define CAN_F5R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F5R1_FB30

#define CAN_F5R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F5R1_FB31

#define CAN_F5R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F5R1_FB4

#define CAN_F5R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F5R1_FB5

#define CAN_F5R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F5R1_FB6

#define CAN_F5R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F5R1_FB7

#define CAN_F5R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F5R1_FB8

#define CAN_F5R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F5R1_FB9

#define CAN_F5R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F5R2_FB0

#define CAN_F5R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F5R2_FB1

#define CAN_F5R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F5R2_FB10

#define CAN_F5R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F5R2_FB11

#define CAN_F5R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F5R2_FB12

#define CAN_F5R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F5R2_FB13

#define CAN_F5R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F5R2_FB14

#define CAN_F5R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F5R2_FB15

#define CAN_F5R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F5R2_FB16

#define CAN_F5R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F5R2_FB17

#define CAN_F5R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F5R2_FB18

#define CAN_F5R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F5R2_FB19

#define CAN_F5R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F5R2_FB2

#define CAN_F5R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F5R2_FB20

#define CAN_F5R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F5R2_FB21

#define CAN_F5R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F5R2_FB22

#define CAN_F5R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F5R2_FB23

#define CAN_F5R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F5R2_FB24

#define CAN_F5R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F5R2_FB25

#define CAN_F5R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F5R2_FB26

#define CAN_F5R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F5R2_FB27

#define CAN_F5R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F5R2_FB28

#define CAN_F5R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F5R2_FB29

#define CAN_F5R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F5R2_FB3

#define CAN_F5R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F5R2_FB30

#define CAN_F5R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F5R2_FB31

#define CAN_F5R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F5R2_FB4

#define CAN_F5R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F5R2_FB5

#define CAN_F5R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F5R2_FB6

#define CAN_F5R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F5R2_FB7

#define CAN_F5R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F5R2_FB8

#define CAN_F5R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F5R2_FB9

#define CAN_F5R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F6R1_FB0

#define CAN_F6R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F6R1_FB1

#define CAN_F6R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F6R1_FB10

#define CAN_F6R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F6R1_FB11

#define CAN_F6R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F6R1_FB12

#define CAN_F6R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F6R1_FB13

#define CAN_F6R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F6R1_FB14

#define CAN_F6R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F6R1_FB15

#define CAN_F6R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F6R1_FB16

#define CAN_F6R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F6R1_FB17

#define CAN_F6R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F6R1_FB18

#define CAN_F6R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F6R1_FB19

#define CAN_F6R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F6R1_FB2

#define CAN_F6R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F6R1_FB20

#define CAN_F6R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F6R1_FB21

#define CAN_F6R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F6R1_FB22

#define CAN_F6R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F6R1_FB23

#define CAN_F6R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F6R1_FB24

#define CAN_F6R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F6R1_FB25

#define CAN_F6R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F6R1_FB26

#define CAN_F6R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F6R1_FB27

#define CAN_F6R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F6R1_FB28

#define CAN_F6R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F6R1_FB29

#define CAN_F6R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F6R1_FB3

#define CAN_F6R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F6R1_FB30

#define CAN_F6R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F6R1_FB31

#define CAN_F6R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F6R1_FB4

#define CAN_F6R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F6R1_FB5

#define CAN_F6R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F6R1_FB6

#define CAN_F6R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F6R1_FB7

#define CAN_F6R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F6R1_FB8

#define CAN_F6R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F6R1_FB9

#define CAN_F6R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F6R2_FB0

#define CAN_F6R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F6R2_FB1

#define CAN_F6R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F6R2_FB10

#define CAN_F6R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F6R2_FB11

#define CAN_F6R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F6R2_FB12

#define CAN_F6R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F6R2_FB13

#define CAN_F6R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F6R2_FB14

#define CAN_F6R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F6R2_FB15

#define CAN_F6R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F6R2_FB16

#define CAN_F6R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F6R2_FB17

#define CAN_F6R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F6R2_FB18

#define CAN_F6R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F6R2_FB19

#define CAN_F6R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F6R2_FB2

#define CAN_F6R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F6R2_FB20

#define CAN_F6R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F6R2_FB21

#define CAN_F6R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F6R2_FB22

#define CAN_F6R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F6R2_FB23

#define CAN_F6R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F6R2_FB24

#define CAN_F6R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F6R2_FB25

#define CAN_F6R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F6R2_FB26

#define CAN_F6R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F6R2_FB27

#define CAN_F6R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F6R2_FB28

#define CAN_F6R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F6R2_FB29

#define CAN_F6R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F6R2_FB3

#define CAN_F6R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F6R2_FB30

#define CAN_F6R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F6R2_FB31

#define CAN_F6R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F6R2_FB4

#define CAN_F6R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F6R2_FB5

#define CAN_F6R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F6R2_FB6

#define CAN_F6R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F6R2_FB7

#define CAN_F6R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F6R2_FB8

#define CAN_F6R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F6R2_FB9

#define CAN_F6R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F7R1_FB0

#define CAN_F7R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F7R1_FB1

#define CAN_F7R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F7R1_FB10

#define CAN_F7R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F7R1_FB11

#define CAN_F7R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F7R1_FB12

#define CAN_F7R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F7R1_FB13

#define CAN_F7R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F7R1_FB14

#define CAN_F7R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F7R1_FB15

#define CAN_F7R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F7R1_FB16

#define CAN_F7R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F7R1_FB17

#define CAN_F7R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F7R1_FB18

#define CAN_F7R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F7R1_FB19

#define CAN_F7R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F7R1_FB2

#define CAN_F7R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F7R1_FB20

#define CAN_F7R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F7R1_FB21

#define CAN_F7R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F7R1_FB22

#define CAN_F7R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F7R1_FB23

#define CAN_F7R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F7R1_FB24

#define CAN_F7R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F7R1_FB25

#define CAN_F7R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F7R1_FB26

#define CAN_F7R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F7R1_FB27

#define CAN_F7R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F7R1_FB28

#define CAN_F7R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F7R1_FB29

#define CAN_F7R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F7R1_FB3

#define CAN_F7R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F7R1_FB30

#define CAN_F7R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F7R1_FB31

#define CAN_F7R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F7R1_FB4

#define CAN_F7R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F7R1_FB5

#define CAN_F7R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F7R1_FB6

#define CAN_F7R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F7R1_FB7

#define CAN_F7R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F7R1_FB8

#define CAN_F7R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F7R1_FB9

#define CAN_F7R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F7R2_FB0

#define CAN_F7R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F7R2_FB1

#define CAN_F7R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F7R2_FB10

#define CAN_F7R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F7R2_FB11

#define CAN_F7R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F7R2_FB12

#define CAN_F7R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F7R2_FB13

#define CAN_F7R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F7R2_FB14

#define CAN_F7R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F7R2_FB15

#define CAN_F7R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F7R2_FB16

#define CAN_F7R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F7R2_FB17

#define CAN_F7R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F7R2_FB18

#define CAN_F7R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F7R2_FB19

#define CAN_F7R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F7R2_FB2

#define CAN_F7R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F7R2_FB20

#define CAN_F7R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F7R2_FB21

#define CAN_F7R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F7R2_FB22

#define CAN_F7R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F7R2_FB23

#define CAN_F7R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F7R2_FB24

#define CAN_F7R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F7R2_FB25

#define CAN_F7R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F7R2_FB26

#define CAN_F7R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F7R2_FB27

#define CAN_F7R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F7R2_FB28

#define CAN_F7R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F7R2_FB29

#define CAN_F7R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F7R2_FB3

#define CAN_F7R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F7R2_FB30

#define CAN_F7R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F7R2_FB31

#define CAN_F7R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F7R2_FB4

#define CAN_F7R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F7R2_FB5

#define CAN_F7R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F7R2_FB6

#define CAN_F7R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F7R2_FB7

#define CAN_F7R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F7R2_FB8

#define CAN_F7R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F7R2_FB9

#define CAN_F7R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F8R1_FB0

#define CAN_F8R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F8R1_FB1

#define CAN_F8R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F8R1_FB10

#define CAN_F8R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F8R1_FB11

#define CAN_F8R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F8R1_FB12

#define CAN_F8R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F8R1_FB13

#define CAN_F8R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F8R1_FB14

#define CAN_F8R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F8R1_FB15

#define CAN_F8R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F8R1_FB16

#define CAN_F8R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F8R1_FB17

#define CAN_F8R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F8R1_FB18

#define CAN_F8R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F8R1_FB19

#define CAN_F8R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F8R1_FB2

#define CAN_F8R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F8R1_FB20

#define CAN_F8R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F8R1_FB21

#define CAN_F8R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F8R1_FB22

#define CAN_F8R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F8R1_FB23

#define CAN_F8R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F8R1_FB24

#define CAN_F8R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F8R1_FB25

#define CAN_F8R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F8R1_FB26

#define CAN_F8R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F8R1_FB27

#define CAN_F8R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F8R1_FB28

#define CAN_F8R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F8R1_FB29

#define CAN_F8R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F8R1_FB3

#define CAN_F8R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F8R1_FB30

#define CAN_F8R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F8R1_FB31

#define CAN_F8R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F8R1_FB4

#define CAN_F8R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F8R1_FB5

#define CAN_F8R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F8R1_FB6

#define CAN_F8R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F8R1_FB7

#define CAN_F8R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F8R1_FB8

#define CAN_F8R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F8R1_FB9

#define CAN_F8R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F8R2_FB0

#define CAN_F8R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F8R2_FB1

#define CAN_F8R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F8R2_FB10

#define CAN_F8R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F8R2_FB11

#define CAN_F8R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F8R2_FB12

#define CAN_F8R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F8R2_FB13

#define CAN_F8R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F8R2_FB14

#define CAN_F8R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F8R2_FB15

#define CAN_F8R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F8R2_FB16

#define CAN_F8R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F8R2_FB17

#define CAN_F8R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F8R2_FB18

#define CAN_F8R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F8R2_FB19

#define CAN_F8R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F8R2_FB2

#define CAN_F8R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F8R2_FB20

#define CAN_F8R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F8R2_FB21

#define CAN_F8R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F8R2_FB22

#define CAN_F8R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F8R2_FB23

#define CAN_F8R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F8R2_FB24

#define CAN_F8R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F8R2_FB25

#define CAN_F8R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F8R2_FB26

#define CAN_F8R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F8R2_FB27

#define CAN_F8R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F8R2_FB28

#define CAN_F8R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F8R2_FB29

#define CAN_F8R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F8R2_FB3

#define CAN_F8R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F8R2_FB30

#define CAN_F8R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F8R2_FB31

#define CAN_F8R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F8R2_FB4

#define CAN_F8R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F8R2_FB5

#define CAN_F8R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F8R2_FB6

#define CAN_F8R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F8R2_FB7

#define CAN_F8R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F8R2_FB8

#define CAN_F8R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F8R2_FB9

#define CAN_F8R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F9R1_FB0

#define CAN_F9R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F9R1_FB1

#define CAN_F9R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F9R1_FB10

#define CAN_F9R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F9R1_FB11

#define CAN_F9R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F9R1_FB12

#define CAN_F9R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F9R1_FB13

#define CAN_F9R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F9R1_FB14

#define CAN_F9R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F9R1_FB15

#define CAN_F9R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F9R1_FB16

#define CAN_F9R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F9R1_FB17

#define CAN_F9R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F9R1_FB18

#define CAN_F9R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F9R1_FB19

#define CAN_F9R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F9R1_FB2

#define CAN_F9R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F9R1_FB20

#define CAN_F9R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F9R1_FB21

#define CAN_F9R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F9R1_FB22

#define CAN_F9R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F9R1_FB23

#define CAN_F9R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F9R1_FB24

#define CAN_F9R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F9R1_FB25

#define CAN_F9R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F9R1_FB26

#define CAN_F9R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F9R1_FB27

#define CAN_F9R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F9R1_FB28

#define CAN_F9R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F9R1_FB29

#define CAN_F9R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F9R1_FB3

#define CAN_F9R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F9R1_FB30

#define CAN_F9R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F9R1_FB31

#define CAN_F9R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F9R1_FB4

#define CAN_F9R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F9R1_FB5

#define CAN_F9R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F9R1_FB6

#define CAN_F9R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F9R1_FB7

#define CAN_F9R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F9R1_FB8

#define CAN_F9R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F9R1_FB9

#define CAN_F9R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_F9R2_FB0

#define CAN_F9R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

◆ CAN_F9R2_FB1

#define CAN_F9R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

◆ CAN_F9R2_FB10

#define CAN_F9R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

◆ CAN_F9R2_FB11

#define CAN_F9R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

◆ CAN_F9R2_FB12

#define CAN_F9R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

◆ CAN_F9R2_FB13

#define CAN_F9R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

◆ CAN_F9R2_FB14

#define CAN_F9R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

◆ CAN_F9R2_FB15

#define CAN_F9R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

◆ CAN_F9R2_FB16

#define CAN_F9R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

◆ CAN_F9R2_FB17

#define CAN_F9R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

◆ CAN_F9R2_FB18

#define CAN_F9R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

◆ CAN_F9R2_FB19

#define CAN_F9R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

◆ CAN_F9R2_FB2

#define CAN_F9R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

◆ CAN_F9R2_FB20

#define CAN_F9R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

◆ CAN_F9R2_FB21

#define CAN_F9R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

◆ CAN_F9R2_FB22

#define CAN_F9R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

◆ CAN_F9R2_FB23

#define CAN_F9R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

◆ CAN_F9R2_FB24

#define CAN_F9R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

◆ CAN_F9R2_FB25

#define CAN_F9R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

◆ CAN_F9R2_FB26

#define CAN_F9R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

◆ CAN_F9R2_FB27

#define CAN_F9R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

◆ CAN_F9R2_FB28

#define CAN_F9R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

◆ CAN_F9R2_FB29

#define CAN_F9R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

◆ CAN_F9R2_FB3

#define CAN_F9R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

◆ CAN_F9R2_FB30

#define CAN_F9R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

◆ CAN_F9R2_FB31

#define CAN_F9R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

◆ CAN_F9R2_FB4

#define CAN_F9R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

◆ CAN_F9R2_FB5

#define CAN_F9R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

◆ CAN_F9R2_FB6

#define CAN_F9R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

◆ CAN_F9R2_FB7

#define CAN_F9R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

◆ CAN_F9R2_FB8

#define CAN_F9R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

◆ CAN_F9R2_FB9

#define CAN_F9R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

◆ CAN_FA1R_FACT

#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)

Filter Active

◆ CAN_FA1R_FACT0

#define CAN_FA1R_FACT0   ((uint16_t)0x0001)

Filter 0 Active

◆ CAN_FA1R_FACT1

#define CAN_FA1R_FACT1   ((uint16_t)0x0002)

Filter 1 Active

◆ CAN_FA1R_FACT10

#define CAN_FA1R_FACT10   ((uint16_t)0x0400)

Filter 10 Active

◆ CAN_FA1R_FACT11

#define CAN_FA1R_FACT11   ((uint16_t)0x0800)

Filter 11 Active

◆ CAN_FA1R_FACT12

#define CAN_FA1R_FACT12   ((uint16_t)0x1000)

Filter 12 Active

◆ CAN_FA1R_FACT13

#define CAN_FA1R_FACT13   ((uint16_t)0x2000)

Filter 13 Active

◆ CAN_FA1R_FACT2

#define CAN_FA1R_FACT2   ((uint16_t)0x0004)

Filter 2 Active

◆ CAN_FA1R_FACT3

#define CAN_FA1R_FACT3   ((uint16_t)0x0008)

Filter 3 Active

◆ CAN_FA1R_FACT4

#define CAN_FA1R_FACT4   ((uint16_t)0x0010)

Filter 4 Active

◆ CAN_FA1R_FACT5

#define CAN_FA1R_FACT5   ((uint16_t)0x0020)

Filter 5 Active

◆ CAN_FA1R_FACT6

#define CAN_FA1R_FACT6   ((uint16_t)0x0040)

Filter 6 Active

◆ CAN_FA1R_FACT7

#define CAN_FA1R_FACT7   ((uint16_t)0x0080)

Filter 7 Active

◆ CAN_FA1R_FACT8

#define CAN_FA1R_FACT8   ((uint16_t)0x0100)

Filter 8 Active

◆ CAN_FA1R_FACT9

#define CAN_FA1R_FACT9   ((uint16_t)0x0200)

Filter 9 Active

◆ CAN_FFA1R_FFA

#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)

Filter FIFO Assignment

◆ CAN_FFA1R_FFA0

#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)

Filter FIFO Assignment for Filter 0

◆ CAN_FFA1R_FFA1

#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)

Filter FIFO Assignment for Filter 1

◆ CAN_FFA1R_FFA10

#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)

Filter FIFO Assignment for Filter 10

◆ CAN_FFA1R_FFA11

#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)

Filter FIFO Assignment for Filter 11

◆ CAN_FFA1R_FFA12

#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)

Filter FIFO Assignment for Filter 12

◆ CAN_FFA1R_FFA13

#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)

Filter FIFO Assignment for Filter 13

◆ CAN_FFA1R_FFA2

#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)

Filter FIFO Assignment for Filter 2

◆ CAN_FFA1R_FFA3

#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)

Filter FIFO Assignment for Filter 3

◆ CAN_FFA1R_FFA4

#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)

Filter FIFO Assignment for Filter 4

◆ CAN_FFA1R_FFA5

#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)

Filter FIFO Assignment for Filter 5

◆ CAN_FFA1R_FFA6

#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)

Filter FIFO Assignment for Filter 6

◆ CAN_FFA1R_FFA7

#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)

Filter FIFO Assignment for Filter 7

◆ CAN_FFA1R_FFA8

#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)

Filter FIFO Assignment for Filter 8

◆ CAN_FFA1R_FFA9

#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)

Filter FIFO Assignment for Filter 9

◆ CAN_FM1R_FBM

#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)

Filter Mode

◆ CAN_FM1R_FBM0

#define CAN_FM1R_FBM0   ((uint16_t)0x0001)

Filter Init Mode bit 0

◆ CAN_FM1R_FBM1

#define CAN_FM1R_FBM1   ((uint16_t)0x0002)

Filter Init Mode bit 1

◆ CAN_FM1R_FBM10

#define CAN_FM1R_FBM10   ((uint16_t)0x0400)

Filter Init Mode bit 10

◆ CAN_FM1R_FBM11

#define CAN_FM1R_FBM11   ((uint16_t)0x0800)

Filter Init Mode bit 11

◆ CAN_FM1R_FBM12

#define CAN_FM1R_FBM12   ((uint16_t)0x1000)

Filter Init Mode bit 12

◆ CAN_FM1R_FBM13

#define CAN_FM1R_FBM13   ((uint16_t)0x2000)

Filter Init Mode bit 13

◆ CAN_FM1R_FBM2

#define CAN_FM1R_FBM2   ((uint16_t)0x0004)

Filter Init Mode bit 2

◆ CAN_FM1R_FBM3

#define CAN_FM1R_FBM3   ((uint16_t)0x0008)

Filter Init Mode bit 3

◆ CAN_FM1R_FBM4

#define CAN_FM1R_FBM4   ((uint16_t)0x0010)

Filter Init Mode bit 4

◆ CAN_FM1R_FBM5

#define CAN_FM1R_FBM5   ((uint16_t)0x0020)

Filter Init Mode bit 5

◆ CAN_FM1R_FBM6

#define CAN_FM1R_FBM6   ((uint16_t)0x0040)

Filter Init Mode bit 6

◆ CAN_FM1R_FBM7

#define CAN_FM1R_FBM7   ((uint16_t)0x0080)

Filter Init Mode bit 7

◆ CAN_FM1R_FBM8

#define CAN_FM1R_FBM8   ((uint16_t)0x0100)

Filter Init Mode bit 8

◆ CAN_FM1R_FBM9

#define CAN_FM1R_FBM9   ((uint16_t)0x0200)

Filter Init Mode bit 9

◆ CAN_FMR_FINIT

#define CAN_FMR_FINIT   ((uint8_t)0x01)

Filter Init Mode

◆ CAN_FS1R_FSC

#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)

Filter Scale Configuration

◆ CAN_FS1R_FSC0

#define CAN_FS1R_FSC0   ((uint16_t)0x0001)

Filter Scale Configuration bit 0

◆ CAN_FS1R_FSC1

#define CAN_FS1R_FSC1   ((uint16_t)0x0002)

Filter Scale Configuration bit 1

◆ CAN_FS1R_FSC10

#define CAN_FS1R_FSC10   ((uint16_t)0x0400)

Filter Scale Configuration bit 10

◆ CAN_FS1R_FSC11

#define CAN_FS1R_FSC11   ((uint16_t)0x0800)

Filter Scale Configuration bit 11

◆ CAN_FS1R_FSC12

#define CAN_FS1R_FSC12   ((uint16_t)0x1000)

Filter Scale Configuration bit 12

◆ CAN_FS1R_FSC13

#define CAN_FS1R_FSC13   ((uint16_t)0x2000)

Filter Scale Configuration bit 13

◆ CAN_FS1R_FSC2

#define CAN_FS1R_FSC2   ((uint16_t)0x0004)

Filter Scale Configuration bit 2

◆ CAN_FS1R_FSC3

#define CAN_FS1R_FSC3   ((uint16_t)0x0008)

Filter Scale Configuration bit 3

◆ CAN_FS1R_FSC4

#define CAN_FS1R_FSC4   ((uint16_t)0x0010)

Filter Scale Configuration bit 4

◆ CAN_FS1R_FSC5

#define CAN_FS1R_FSC5   ((uint16_t)0x0020)

Filter Scale Configuration bit 5

◆ CAN_FS1R_FSC6

#define CAN_FS1R_FSC6   ((uint16_t)0x0040)

Filter Scale Configuration bit 6

◆ CAN_FS1R_FSC7

#define CAN_FS1R_FSC7   ((uint16_t)0x0080)

Filter Scale Configuration bit 7

◆ CAN_FS1R_FSC8

#define CAN_FS1R_FSC8   ((uint16_t)0x0100)

Filter Scale Configuration bit 8

◆ CAN_FS1R_FSC9

#define CAN_FS1R_FSC9   ((uint16_t)0x0200)

Filter Scale Configuration bit 9

◆ CAN_IER_BOFIE

#define CAN_IER_BOFIE   ((uint32_t)0x00000400)

Bus-Off Interrupt Enable

◆ CAN_IER_EPVIE

#define CAN_IER_EPVIE   ((uint32_t)0x00000200)

Error Passive Interrupt Enable

◆ CAN_IER_ERRIE

#define CAN_IER_ERRIE   ((uint32_t)0x00008000)

Error Interrupt Enable

◆ CAN_IER_EWGIE

#define CAN_IER_EWGIE   ((uint32_t)0x00000100)

Error Warning Interrupt Enable

◆ CAN_IER_FFIE0

#define CAN_IER_FFIE0   ((uint32_t)0x00000004)

FIFO Full Interrupt Enable

◆ CAN_IER_FFIE1

#define CAN_IER_FFIE1   ((uint32_t)0x00000020)

FIFO Full Interrupt Enable

◆ CAN_IER_FMPIE0

#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)

FIFO Message Pending Interrupt Enable

◆ CAN_IER_FMPIE1

#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)

FIFO Message Pending Interrupt Enable

◆ CAN_IER_FOVIE0

#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)

FIFO Overrun Interrupt Enable

◆ CAN_IER_FOVIE1

#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)

FIFO Overrun Interrupt Enable

◆ CAN_IER_LECIE

#define CAN_IER_LECIE   ((uint32_t)0x00000800)

Last Error Code Interrupt Enable

◆ CAN_IER_SLKIE

#define CAN_IER_SLKIE   ((uint32_t)0x00020000)

Sleep Interrupt Enable

◆ CAN_IER_TMEIE

#define CAN_IER_TMEIE   ((uint32_t)0x00000001)

Transmit Mailbox Empty Interrupt Enable

◆ CAN_IER_WKUIE

#define CAN_IER_WKUIE   ((uint32_t)0x00010000)

Wakeup Interrupt Enable

◆ CAN_MCR_ABOM

#define CAN_MCR_ABOM   ((uint16_t)0x0040)

Automatic Bus-Off Management

◆ CAN_MCR_AWUM

#define CAN_MCR_AWUM   ((uint16_t)0x0020)

Automatic Wakeup Mode

◆ CAN_MCR_INRQ

#define CAN_MCR_INRQ   ((uint16_t)0x0001)

<CAN control and status registers Initialization Request

◆ CAN_MCR_NART

#define CAN_MCR_NART   ((uint16_t)0x0010)

No Automatic Retransmission

◆ CAN_MCR_RESET

#define CAN_MCR_RESET   ((uint16_t)0x8000)

bxCAN software master reset

◆ CAN_MCR_RFLM

#define CAN_MCR_RFLM   ((uint16_t)0x0008)

Receive FIFO Locked Mode

◆ CAN_MCR_SLEEP

#define CAN_MCR_SLEEP   ((uint16_t)0x0002)

Sleep Mode Request

◆ CAN_MCR_TTCM

#define CAN_MCR_TTCM   ((uint16_t)0x0080)

Time Triggered Communication Mode

◆ CAN_MCR_TXFP

#define CAN_MCR_TXFP   ((uint16_t)0x0004)

Transmit FIFO Priority

◆ CAN_MSR_ERRI

#define CAN_MSR_ERRI   ((uint16_t)0x0004)

Error Interrupt

◆ CAN_MSR_INAK

#define CAN_MSR_INAK   ((uint16_t)0x0001)

Initialization Acknowledge

◆ CAN_MSR_RX

#define CAN_MSR_RX   ((uint16_t)0x0800)

CAN Rx Signal

◆ CAN_MSR_RXM

#define CAN_MSR_RXM   ((uint16_t)0x0200)

Receive Mode

◆ CAN_MSR_SAMP

#define CAN_MSR_SAMP   ((uint16_t)0x0400)

Last Sample Point

◆ CAN_MSR_SLAK

#define CAN_MSR_SLAK   ((uint16_t)0x0002)

Sleep Acknowledge

◆ CAN_MSR_SLAKI

#define CAN_MSR_SLAKI   ((uint16_t)0x0010)

Sleep Acknowledge Interrupt

◆ CAN_MSR_TXM

#define CAN_MSR_TXM   ((uint16_t)0x0100)

Transmit Mode

◆ CAN_MSR_WKUI

#define CAN_MSR_WKUI   ((uint16_t)0x0008)

Wakeup Interrupt

◆ CAN_RDH0R_DATA4

#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

◆ CAN_RDH0R_DATA5

#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

◆ CAN_RDH0R_DATA6

#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

◆ CAN_RDH0R_DATA7

#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

◆ CAN_RDH1R_DATA4

#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

◆ CAN_RDH1R_DATA5

#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

◆ CAN_RDH1R_DATA6

#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

◆ CAN_RDH1R_DATA7

#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7 CAN filter registers

◆ CAN_RDL0R_DATA0

#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

◆ CAN_RDL0R_DATA1

#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

◆ CAN_RDL0R_DATA2

#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

◆ CAN_RDL0R_DATA3

#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

◆ CAN_RDL1R_DATA0

#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

◆ CAN_RDL1R_DATA1

#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

◆ CAN_RDL1R_DATA2

#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

◆ CAN_RDL1R_DATA3

#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

◆ CAN_RDT0R_DLC

#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

◆ CAN_RDT0R_FMI

#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

◆ CAN_RDT0R_TIME

#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

◆ CAN_RDT1R_DLC

#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

◆ CAN_RDT1R_FMI

#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

◆ CAN_RDT1R_TIME

#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

◆ CAN_RF0R_FMP0

#define CAN_RF0R_FMP0   ((uint8_t)0x03)

FIFO 0 Message Pending

◆ CAN_RF0R_FOVR0

#define CAN_RF0R_FOVR0   ((uint8_t)0x10)

FIFO 0 Overrun

◆ CAN_RF0R_FULL0

#define CAN_RF0R_FULL0   ((uint8_t)0x08)

FIFO 0 Full

◆ CAN_RF0R_RFOM0

#define CAN_RF0R_RFOM0   ((uint8_t)0x20)

Release FIFO 0 Output Mailbox

◆ CAN_RF1R_FMP1

#define CAN_RF1R_FMP1   ((uint8_t)0x03)

FIFO 1 Message Pending

◆ CAN_RF1R_FOVR1

#define CAN_RF1R_FOVR1   ((uint8_t)0x10)

FIFO 1 Overrun

◆ CAN_RF1R_FULL1

#define CAN_RF1R_FULL1   ((uint8_t)0x08)

FIFO 1 Full

◆ CAN_RF1R_RFOM1

#define CAN_RF1R_RFOM1   ((uint8_t)0x20)

Release FIFO 1 Output Mailbox

◆ CAN_RI0R_EXID

#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

◆ CAN_RI0R_IDE

#define CAN_RI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

◆ CAN_RI0R_RTR

#define CAN_RI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

◆ CAN_RI0R_STID

#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

◆ CAN_RI1R_EXID

#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

◆ CAN_RI1R_IDE

#define CAN_RI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

◆ CAN_RI1R_RTR

#define CAN_RI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

◆ CAN_RI1R_STID

#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

◆ CAN_TDH0R_DATA4

#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

◆ CAN_TDH0R_DATA5

#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

◆ CAN_TDH0R_DATA6

#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

◆ CAN_TDH0R_DATA7

#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

◆ CAN_TDH1R_DATA4

#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

◆ CAN_TDH1R_DATA5

#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

◆ CAN_TDH1R_DATA6

#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

◆ CAN_TDH1R_DATA7

#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

◆ CAN_TDH2R_DATA4

#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

◆ CAN_TDH2R_DATA5

#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

◆ CAN_TDH2R_DATA6

#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

◆ CAN_TDH2R_DATA7

#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

◆ CAN_TDL0R_DATA0

#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

◆ CAN_TDL0R_DATA1

#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

◆ CAN_TDL0R_DATA2

#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

◆ CAN_TDL0R_DATA3

#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

◆ CAN_TDL1R_DATA0

#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

◆ CAN_TDL1R_DATA1

#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

◆ CAN_TDL1R_DATA2

#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

◆ CAN_TDL1R_DATA3

#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

◆ CAN_TDL2R_DATA0

#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

◆ CAN_TDL2R_DATA1

#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

◆ CAN_TDL2R_DATA2

#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

◆ CAN_TDL2R_DATA3

#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

◆ CAN_TDT0R_DLC

#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

◆ CAN_TDT0R_TGT

#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

◆ CAN_TDT0R_TIME

#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

◆ CAN_TDT1R_DLC

#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

◆ CAN_TDT1R_TGT

#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

◆ CAN_TDT1R_TIME

#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

◆ CAN_TDT2R_DLC

#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)

Data Length Code

◆ CAN_TDT2R_TGT

#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

◆ CAN_TDT2R_TIME

#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

◆ CAN_TI0R_EXID

#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

◆ CAN_TI0R_IDE

#define CAN_TI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

◆ CAN_TI0R_RTR

#define CAN_TI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

◆ CAN_TI0R_STID

#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

◆ CAN_TI0R_TXRQ

#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

◆ CAN_TI1R_EXID

#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

◆ CAN_TI1R_IDE

#define CAN_TI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

◆ CAN_TI1R_RTR

#define CAN_TI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

◆ CAN_TI1R_STID

#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

◆ CAN_TI1R_TXRQ

#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

◆ CAN_TI2R_EXID

#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

◆ CAN_TI2R_IDE

#define CAN_TI2R_IDE   ((uint32_t)0x00000004)

Identifier Extension

◆ CAN_TI2R_RTR

#define CAN_TI2R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

◆ CAN_TI2R_STID

#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

◆ CAN_TI2R_TXRQ

#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

◆ CAN_TSR_ABRQ0

#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)

Abort Request for Mailbox0

◆ CAN_TSR_ABRQ1

#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)

Abort Request for Mailbox 1

◆ CAN_TSR_ABRQ2

#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)

Abort Request for Mailbox 2

◆ CAN_TSR_ALST0

#define CAN_TSR_ALST0   ((uint32_t)0x00000004)

Arbitration Lost for Mailbox0

◆ CAN_TSR_ALST1

#define CAN_TSR_ALST1   ((uint32_t)0x00000400)

Arbitration Lost for Mailbox1

◆ CAN_TSR_ALST2

#define CAN_TSR_ALST2   ((uint32_t)0x00040000)

Arbitration Lost for mailbox 2

◆ CAN_TSR_CODE

#define CAN_TSR_CODE   ((uint32_t)0x03000000)

Mailbox Code

◆ CAN_TSR_LOW

#define CAN_TSR_LOW   ((uint32_t)0xE0000000)

LOW[2:0] bits

◆ CAN_TSR_LOW0

#define CAN_TSR_LOW0   ((uint32_t)0x20000000)

Lowest Priority Flag for Mailbox 0

◆ CAN_TSR_LOW1

#define CAN_TSR_LOW1   ((uint32_t)0x40000000)

Lowest Priority Flag for Mailbox 1

◆ CAN_TSR_LOW2

#define CAN_TSR_LOW2   ((uint32_t)0x80000000)

Lowest Priority Flag for Mailbox 2

◆ CAN_TSR_RQCP0

#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)

Request Completed Mailbox0

◆ CAN_TSR_RQCP1

#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)

Request Completed Mailbox1

◆ CAN_TSR_RQCP2

#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)

Request Completed Mailbox2

◆ CAN_TSR_TERR0

#define CAN_TSR_TERR0   ((uint32_t)0x00000008)

Transmission Error of Mailbox0

◆ CAN_TSR_TERR1

#define CAN_TSR_TERR1   ((uint32_t)0x00000800)

Transmission Error of Mailbox1

◆ CAN_TSR_TERR2

#define CAN_TSR_TERR2   ((uint32_t)0x00080000)

Transmission Error of Mailbox 2

◆ CAN_TSR_TME

#define CAN_TSR_TME   ((uint32_t)0x1C000000)

TME[2:0] bits

◆ CAN_TSR_TME0

#define CAN_TSR_TME0   ((uint32_t)0x04000000)

Transmit Mailbox 0 Empty

◆ CAN_TSR_TME1

#define CAN_TSR_TME1   ((uint32_t)0x08000000)

Transmit Mailbox 1 Empty

◆ CAN_TSR_TME2

#define CAN_TSR_TME2   ((uint32_t)0x10000000)

Transmit Mailbox 2 Empty

◆ CAN_TSR_TXOK0

#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)

Transmission OK of Mailbox0

◆ CAN_TSR_TXOK1

#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)

Transmission OK of Mailbox1

◆ CAN_TSR_TXOK2

#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)

Transmission OK of Mailbox 2

◆ CRC_CR_RESET

#define CRC_CR_RESET   ((uint8_t)0x01)

RESET bit

◆ CRC_DR_DR

#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)

Data register bits

◆ CRC_IDR_IDR

#define CRC_IDR_IDR   ((uint8_t)0xFF)

General-purpose 8-bit data register bits

◆ CRYP_CR_ALGODIR

#define CRYP_CR_ALGODIR   ((uint32_t)0x00000004)

◆ CRYP_CR_ALGOMODE

#define CRYP_CR_ALGOMODE   ((uint32_t)0x00000038)

◆ CRYP_CR_ALGOMODE_0

#define CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)

◆ CRYP_CR_ALGOMODE_1

#define CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)

◆ CRYP_CR_ALGOMODE_2

#define CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)

◆ CRYP_CR_ALGOMODE_AES_CBC

#define CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)

◆ CRYP_CR_ALGOMODE_AES_CTR

#define CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)

◆ CRYP_CR_ALGOMODE_AES_ECB

#define CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)

◆ CRYP_CR_ALGOMODE_AES_KEY

#define CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)

◆ CRYP_CR_ALGOMODE_DES_CBC

#define CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)

◆ CRYP_CR_ALGOMODE_DES_ECB

#define CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)

◆ CRYP_CR_ALGOMODE_TDES_CBC

#define CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)

◆ CRYP_CR_ALGOMODE_TDES_ECB

#define CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)

◆ CRYP_CR_CRYPEN

#define CRYP_CR_CRYPEN   ((uint32_t)0x00008000)

◆ CRYP_CR_DATATYPE

#define CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)

◆ CRYP_CR_DATATYPE_0

#define CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)

◆ CRYP_CR_DATATYPE_1

#define CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)

◆ CRYP_CR_FFLUSH

#define CRYP_CR_FFLUSH   ((uint32_t)0x00004000)

◆ CRYP_CR_KEYSIZE

#define CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)

◆ CRYP_CR_KEYSIZE_0

#define CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)

◆ CRYP_CR_KEYSIZE_1

#define CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)

◆ CRYP_DMACR_DIEN

#define CRYP_DMACR_DIEN   ((uint32_t)0x00000001)

◆ CRYP_DMACR_DOEN

#define CRYP_DMACR_DOEN   ((uint32_t)0x00000002)

◆ CRYP_IMSCR_INIM

#define CRYP_IMSCR_INIM   ((uint32_t)0x00000001)

◆ CRYP_IMSCR_OUTIM

#define CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)

◆ CRYP_MISR_INMIS

#define CRYP_MISR_INMIS   ((uint32_t)0x00000001)

◆ CRYP_MISR_OUTMIS

#define CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)

◆ CRYP_RISR_INRIS

#define CRYP_RISR_INRIS   ((uint32_t)0x00000002)

◆ CRYP_RISR_OUTRIS

#define CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)

◆ CRYP_SR_BUSY

#define CRYP_SR_BUSY   ((uint32_t)0x00000010)

◆ CRYP_SR_IFEM

#define CRYP_SR_IFEM   ((uint32_t)0x00000001)

◆ CRYP_SR_IFNF

#define CRYP_SR_IFNF   ((uint32_t)0x00000002)

◆ CRYP_SR_OFFU

#define CRYP_SR_OFFU   ((uint32_t)0x00000008)

◆ CRYP_SR_OFNE

#define CRYP_SR_OFNE   ((uint32_t)0x00000004)

◆ DAC_CR_BOFF1

#define DAC_CR_BOFF1   ((uint32_t)0x00000002)

DAC channel1 output buffer disable

◆ DAC_CR_BOFF2

#define DAC_CR_BOFF2   ((uint32_t)0x00020000)

DAC channel2 output buffer disable

◆ DAC_CR_DMAEN1

#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)

DAC channel1 DMA enable

◆ DAC_CR_DMAEN2

#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)

DAC channel2 DMA enabled

◆ DAC_CR_EN1

#define DAC_CR_EN1   ((uint32_t)0x00000001)

DAC channel1 enable

◆ DAC_CR_EN2

#define DAC_CR_EN2   ((uint32_t)0x00010000)

DAC channel2 enable

◆ DAC_CR_MAMP1

#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

◆ DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)

Bit 0

◆ DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)

Bit 1

◆ DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)

Bit 2

◆ DAC_CR_MAMP1_3

#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)

Bit 3

◆ DAC_CR_MAMP2

#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

◆ DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)

Bit 0

◆ DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)

Bit 1

◆ DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)

Bit 2

◆ DAC_CR_MAMP2_3

#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)

Bit 3

◆ DAC_CR_TEN1

#define DAC_CR_TEN1   ((uint32_t)0x00000004)

DAC channel1 Trigger enable

◆ DAC_CR_TEN2

#define DAC_CR_TEN2   ((uint32_t)0x00040000)

DAC channel2 Trigger enable

◆ DAC_CR_TSEL1

#define DAC_CR_TSEL1   ((uint32_t)0x00000038)

TSEL1[2:0] (DAC channel1 Trigger selection)

◆ DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)

Bit 0

◆ DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)

Bit 1

◆ DAC_CR_TSEL1_2

#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)

Bit 2

◆ DAC_CR_TSEL2

#define DAC_CR_TSEL2   ((uint32_t)0x00380000)

TSEL2[2:0] (DAC channel2 Trigger selection)

◆ DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)

Bit 0

◆ DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)

Bit 1

◆ DAC_CR_TSEL2_2

#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)

Bit 2

◆ DAC_CR_WAVE1

#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

◆ DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)

Bit 0

◆ DAC_CR_WAVE1_1

#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)

Bit 1

◆ DAC_CR_WAVE2

#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

◆ DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)

Bit 0

◆ DAC_CR_WAVE2_1

#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)

Bit 1

◆ DAC_DHR12L1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12L2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12LD_DACC2DHR

#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12R1_DACC1DHR

#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12R2_DACC2DHR

#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)

DAC channel2 12-bit Right aligned data

◆ DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12RD_DACC2DHR

#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)

DAC channel2 12-bit Right aligned data

◆ DAC_DHR8R1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8R2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)

DAC channel2 8-bit Right aligned data

◆ DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8RD_DACC2DHR

#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)

DAC channel2 8-bit Right aligned data

◆ DAC_DOR1_DACC1DOR

#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)

DAC channel1 data output

◆ DAC_DOR2_DACC2DOR

#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)

DAC channel2 data output

◆ DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)

DAC channel1 DMA underrun flag

◆ DAC_SR_DMAUDR2

#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)

DAC channel2 DMA underrun flag

◆ DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)

DAC channel1 software trigger

◆ DAC_SWTRIGR_SWTRIG2

#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)

DAC channel2 software trigger

◆ DBGMCU_APB1_FZ_DBG_CAN1_STOP

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)

◆ DBGMCU_APB1_FZ_DBG_CAN2_STOP

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)

◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)

◆ DBGMCU_APB1_FZ_DBG_IWDEG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)

◆ DBGMCU_APB1_FZ_DBG_TIM10_STOP

#define DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)

◆ DBGMCU_APB1_FZ_DBG_TIM11_STOP

#define DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)

◆ DBGMCU_APB1_FZ_DBG_TIM12_STOP

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)

◆ DBGMCU_APB1_FZ_DBG_TIM13_STOP

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)

◆ DBGMCU_APB1_FZ_DBG_TIM14_STOP

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)

◆ DBGMCU_APB1_FZ_DBG_TIM1_STOP

#define DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)

◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)

◆ DBGMCU_APB1_FZ_DBG_TIM8_STOP

#define DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)

◆ DBGMCU_APB1_FZ_DBG_TIM9_STOP

#define DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)

◆ DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)

◆ DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)

◆ DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)

◆ DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)

◆ DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)

◆ DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040

Bit 0

◆ DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080

Bit 1

◆ DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)

◆ DBGMCU_IDCODE_REV_ID

#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)

◆ DCMI_CR_CAPTURE

#define DCMI_CR_CAPTURE   ((uint32_t)0x00000001)

◆ DCMI_CR_CM

#define DCMI_CR_CM   ((uint32_t)0x00000002)

◆ DCMI_CR_CRE

#define DCMI_CR_CRE   ((uint32_t)0x00001000)

◆ DCMI_CR_CROP

#define DCMI_CR_CROP   ((uint32_t)0x00000004)

◆ DCMI_CR_EDM_0

#define DCMI_CR_EDM_0   ((uint32_t)0x00000400)

◆ DCMI_CR_EDM_1

#define DCMI_CR_EDM_1   ((uint32_t)0x00000800)

◆ DCMI_CR_ENABLE

#define DCMI_CR_ENABLE   ((uint32_t)0x00004000)

◆ DCMI_CR_ESS

#define DCMI_CR_ESS   ((uint32_t)0x00000010)

◆ DCMI_CR_FCRC_0

#define DCMI_CR_FCRC_0   ((uint32_t)0x00000100)

◆ DCMI_CR_FCRC_1

#define DCMI_CR_FCRC_1   ((uint32_t)0x00000200)

◆ DCMI_CR_HSPOL

#define DCMI_CR_HSPOL   ((uint32_t)0x00000040)

◆ DCMI_CR_JPEG

#define DCMI_CR_JPEG   ((uint32_t)0x00000008)

◆ DCMI_CR_PCKPOL

#define DCMI_CR_PCKPOL   ((uint32_t)0x00000020)

◆ DCMI_CR_VSPOL

#define DCMI_CR_VSPOL   ((uint32_t)0x00000080)

◆ DCMI_ICR_ERR_ISC

#define DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)

◆ DCMI_ICR_FRAME_ISC

#define DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)

◆ DCMI_ICR_LINE_ISC

#define DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)

◆ DCMI_ICR_OVF_ISC

#define DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)

◆ DCMI_ICR_VSYNC_ISC

#define DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)

◆ DCMI_IER_ERR_IE

#define DCMI_IER_ERR_IE   ((uint32_t)0x00000004)

◆ DCMI_IER_FRAME_IE

#define DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)

◆ DCMI_IER_LINE_IE

#define DCMI_IER_LINE_IE   ((uint32_t)0x00000010)

◆ DCMI_IER_OVF_IE

#define DCMI_IER_OVF_IE   ((uint32_t)0x00000002)

◆ DCMI_IER_VSYNC_IE

#define DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)

◆ DCMI_MISR_ERR_MIS

#define DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)

◆ DCMI_MISR_FRAME_MIS

#define DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)

◆ DCMI_MISR_LINE_MIS

#define DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)

◆ DCMI_MISR_OVF_MIS

#define DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)

◆ DCMI_MISR_VSYNC_MIS

#define DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)

◆ DCMI_RISR_ERR_RIS

#define DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)

◆ DCMI_RISR_FRAME_RIS

#define DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)

◆ DCMI_RISR_LINE_RIS

#define DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)

◆ DCMI_RISR_OVF_RIS

#define DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)

◆ DCMI_RISR_VSYNC_RIS

#define DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)

◆ DCMI_SR_FNE

#define DCMI_SR_FNE   ((uint32_t)0x00000004)

◆ DCMI_SR_HSYNC

#define DCMI_SR_HSYNC   ((uint32_t)0x00000001)

◆ DCMI_SR_VSYNC

#define DCMI_SR_VSYNC   ((uint32_t)0x00000002)

◆ DMA_HIFCR_CDMEIF4

#define DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)

◆ DMA_HIFCR_CDMEIF5

#define DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)

◆ DMA_HIFCR_CDMEIF6

#define DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)

◆ DMA_HIFCR_CDMEIF7

#define DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)

◆ DMA_HIFCR_CFEIF4

#define DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)

◆ DMA_HIFCR_CFEIF5

#define DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)

◆ DMA_HIFCR_CFEIF6

#define DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)

◆ DMA_HIFCR_CFEIF7

#define DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)

◆ DMA_HIFCR_CHTIF4

#define DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)

◆ DMA_HIFCR_CHTIF5

#define DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)

◆ DMA_HIFCR_CHTIF6

#define DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)

◆ DMA_HIFCR_CHTIF7

#define DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)

◆ DMA_HIFCR_CTCIF4

#define DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)

◆ DMA_HIFCR_CTCIF5

#define DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)

◆ DMA_HIFCR_CTCIF6

#define DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)

◆ DMA_HIFCR_CTCIF7

#define DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)

◆ DMA_HIFCR_CTEIF4

#define DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)

◆ DMA_HIFCR_CTEIF5

#define DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)

◆ DMA_HIFCR_CTEIF6

#define DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)

◆ DMA_HIFCR_CTEIF7

#define DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)

◆ DMA_HISR_DMEIF4

#define DMA_HISR_DMEIF4   ((uint32_t)0x00000004)

◆ DMA_HISR_DMEIF5

#define DMA_HISR_DMEIF5   ((uint32_t)0x00000100)

◆ DMA_HISR_DMEIF6

#define DMA_HISR_DMEIF6   ((uint32_t)0x00040000)

◆ DMA_HISR_DMEIF7

#define DMA_HISR_DMEIF7   ((uint32_t)0x01000000)

◆ DMA_HISR_FEIF4

#define DMA_HISR_FEIF4   ((uint32_t)0x00000001)

◆ DMA_HISR_FEIF5

#define DMA_HISR_FEIF5   ((uint32_t)0x00000040)

◆ DMA_HISR_FEIF6

#define DMA_HISR_FEIF6   ((uint32_t)0x00010000)

◆ DMA_HISR_FEIF7

#define DMA_HISR_FEIF7   ((uint32_t)0x00400000)

◆ DMA_HISR_HTIF4

#define DMA_HISR_HTIF4   ((uint32_t)0x00000010)

◆ DMA_HISR_HTIF5

#define DMA_HISR_HTIF5   ((uint32_t)0x00000400)

◆ DMA_HISR_HTIF6

#define DMA_HISR_HTIF6   ((uint32_t)0x00100000)

◆ DMA_HISR_HTIF7

#define DMA_HISR_HTIF7   ((uint32_t)0x04000000)

◆ DMA_HISR_TCIF4

#define DMA_HISR_TCIF4   ((uint32_t)0x00000020)

◆ DMA_HISR_TCIF5

#define DMA_HISR_TCIF5   ((uint32_t)0x00000800)

◆ DMA_HISR_TCIF6

#define DMA_HISR_TCIF6   ((uint32_t)0x00200000)

◆ DMA_HISR_TCIF7

#define DMA_HISR_TCIF7   ((uint32_t)0x08000000)

◆ DMA_HISR_TEIF4

#define DMA_HISR_TEIF4   ((uint32_t)0x00000008)

◆ DMA_HISR_TEIF5

#define DMA_HISR_TEIF5   ((uint32_t)0x00000200)

◆ DMA_HISR_TEIF6

#define DMA_HISR_TEIF6   ((uint32_t)0x00080000)

◆ DMA_HISR_TEIF7

#define DMA_HISR_TEIF7   ((uint32_t)0x02000000)

◆ DMA_LIFCR_CDMEIF0

#define DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)

◆ DMA_LIFCR_CDMEIF1

#define DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)

◆ DMA_LIFCR_CDMEIF2

#define DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)

◆ DMA_LIFCR_CDMEIF3

#define DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)

◆ DMA_LIFCR_CFEIF0

#define DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)

◆ DMA_LIFCR_CFEIF1

#define DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)

◆ DMA_LIFCR_CFEIF2

#define DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)

◆ DMA_LIFCR_CFEIF3

#define DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)

◆ DMA_LIFCR_CHTIF0

#define DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)

◆ DMA_LIFCR_CHTIF1

#define DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)

◆ DMA_LIFCR_CHTIF2

#define DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)

◆ DMA_LIFCR_CHTIF3

#define DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)

◆ DMA_LIFCR_CTCIF0

#define DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)

◆ DMA_LIFCR_CTCIF1

#define DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)

◆ DMA_LIFCR_CTCIF2

#define DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)

◆ DMA_LIFCR_CTCIF3

#define DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)

◆ DMA_LIFCR_CTEIF0

#define DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)

◆ DMA_LIFCR_CTEIF1

#define DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)

◆ DMA_LIFCR_CTEIF2

#define DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)

◆ DMA_LIFCR_CTEIF3

#define DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)

◆ DMA_LISR_DMEIF0

#define DMA_LISR_DMEIF0   ((uint32_t)0x00000004)

◆ DMA_LISR_DMEIF1

#define DMA_LISR_DMEIF1   ((uint32_t)0x00000100)

◆ DMA_LISR_DMEIF2

#define DMA_LISR_DMEIF2   ((uint32_t)0x00040000)

◆ DMA_LISR_DMEIF3

#define DMA_LISR_DMEIF3   ((uint32_t)0x01000000)

◆ DMA_LISR_FEIF0

#define DMA_LISR_FEIF0   ((uint32_t)0x00000001)

◆ DMA_LISR_FEIF1

#define DMA_LISR_FEIF1   ((uint32_t)0x00000040)

◆ DMA_LISR_FEIF2

#define DMA_LISR_FEIF2   ((uint32_t)0x00010000)

◆ DMA_LISR_FEIF3

#define DMA_LISR_FEIF3   ((uint32_t)0x00400000)

◆ DMA_LISR_HTIF0

#define DMA_LISR_HTIF0   ((uint32_t)0x00000010)

◆ DMA_LISR_HTIF1

#define DMA_LISR_HTIF1   ((uint32_t)0x00000400)

◆ DMA_LISR_HTIF2

#define DMA_LISR_HTIF2   ((uint32_t)0x00100000)

◆ DMA_LISR_HTIF3

#define DMA_LISR_HTIF3   ((uint32_t)0x04000000)

◆ DMA_LISR_TCIF0

#define DMA_LISR_TCIF0   ((uint32_t)0x00000020)

◆ DMA_LISR_TCIF1

#define DMA_LISR_TCIF1   ((uint32_t)0x00000800)

◆ DMA_LISR_TCIF2

#define DMA_LISR_TCIF2   ((uint32_t)0x00200000)

◆ DMA_LISR_TCIF3

#define DMA_LISR_TCIF3   ((uint32_t)0x08000000)

◆ DMA_LISR_TEIF0

#define DMA_LISR_TEIF0   ((uint32_t)0x00000008)

◆ DMA_LISR_TEIF1

#define DMA_LISR_TEIF1   ((uint32_t)0x00000200)

◆ DMA_LISR_TEIF2

#define DMA_LISR_TEIF2   ((uint32_t)0x00080000)

◆ DMA_LISR_TEIF3

#define DMA_LISR_TEIF3   ((uint32_t)0x02000000)

◆ DMA_SxCR_ACK

#define DMA_SxCR_ACK   ((uint32_t)0x00100000)

◆ DMA_SxCR_CHSEL

#define DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)

◆ DMA_SxCR_CHSEL_0

#define DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)

◆ DMA_SxCR_CHSEL_1

#define DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)

◆ DMA_SxCR_CHSEL_2

#define DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)

◆ DMA_SxCR_CIRC

#define DMA_SxCR_CIRC   ((uint32_t)0x00000100)

◆ DMA_SxCR_CT

#define DMA_SxCR_CT   ((uint32_t)0x00080000)

◆ DMA_SxCR_DBM

#define DMA_SxCR_DBM   ((uint32_t)0x00040000)

◆ DMA_SxCR_DIR

#define DMA_SxCR_DIR   ((uint32_t)0x000000C0)

◆ DMA_SxCR_DIR_0

#define DMA_SxCR_DIR_0   ((uint32_t)0x00000040)

◆ DMA_SxCR_DIR_1

#define DMA_SxCR_DIR_1   ((uint32_t)0x00000080)

◆ DMA_SxCR_DMEIE

#define DMA_SxCR_DMEIE   ((uint32_t)0x00000002)

◆ DMA_SxCR_EN

#define DMA_SxCR_EN   ((uint32_t)0x00000001)

◆ DMA_SxCR_HTIE

#define DMA_SxCR_HTIE   ((uint32_t)0x00000008)

◆ DMA_SxCR_MBURST

#define DMA_SxCR_MBURST   ((uint32_t)0x01800000)

◆ DMA_SxCR_MBURST_0

#define DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)

◆ DMA_SxCR_MBURST_1

#define DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)

◆ DMA_SxCR_MINC

#define DMA_SxCR_MINC   ((uint32_t)0x00000400)

◆ DMA_SxCR_MSIZE

#define DMA_SxCR_MSIZE   ((uint32_t)0x00006000)

◆ DMA_SxCR_MSIZE_0

#define DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)

◆ DMA_SxCR_MSIZE_1

#define DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)

◆ DMA_SxCR_PBURST

#define DMA_SxCR_PBURST   ((uint32_t)0x00600000)

◆ DMA_SxCR_PBURST_0

#define DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)

◆ DMA_SxCR_PBURST_1

#define DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)

◆ DMA_SxCR_PFCTRL

#define DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)

◆ DMA_SxCR_PINC

#define DMA_SxCR_PINC   ((uint32_t)0x00000200)

◆ DMA_SxCR_PINCOS

#define DMA_SxCR_PINCOS   ((uint32_t)0x00008000)

◆ DMA_SxCR_PL

#define DMA_SxCR_PL   ((uint32_t)0x00030000)

◆ DMA_SxCR_PL_0

#define DMA_SxCR_PL_0   ((uint32_t)0x00010000)

◆ DMA_SxCR_PL_1

#define DMA_SxCR_PL_1   ((uint32_t)0x00020000)

◆ DMA_SxCR_PSIZE

#define DMA_SxCR_PSIZE   ((uint32_t)0x00001800)

◆ DMA_SxCR_PSIZE_0

#define DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)

◆ DMA_SxCR_PSIZE_1

#define DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)

◆ DMA_SxCR_TCIE

#define DMA_SxCR_TCIE   ((uint32_t)0x00000010)

◆ DMA_SxCR_TEIE

#define DMA_SxCR_TEIE   ((uint32_t)0x00000004)

◆ DMA_SxFCR_DMDIS

#define DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)

◆ DMA_SxFCR_FEIE

#define DMA_SxFCR_FEIE   ((uint32_t)0x00000080)

◆ DMA_SxFCR_FS

#define DMA_SxFCR_FS   ((uint32_t)0x00000038)

◆ DMA_SxFCR_FS_0

#define DMA_SxFCR_FS_0   ((uint32_t)0x00000008)

◆ DMA_SxFCR_FS_1

#define DMA_SxFCR_FS_1   ((uint32_t)0x00000010)

◆ DMA_SxFCR_FS_2

#define DMA_SxFCR_FS_2   ((uint32_t)0x00000020)

◆ DMA_SxFCR_FTH

#define DMA_SxFCR_FTH   ((uint32_t)0x00000003)

◆ DMA_SxFCR_FTH_0

#define DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)

◆ DMA_SxFCR_FTH_1

#define DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)

◆ DMA_SxNDT

#define DMA_SxNDT   ((uint32_t)0x0000FFFF)

◆ DMA_SxNDT_0

#define DMA_SxNDT_0   ((uint32_t)0x00000001)

◆ DMA_SxNDT_1

#define DMA_SxNDT_1   ((uint32_t)0x00000002)

◆ DMA_SxNDT_10

#define DMA_SxNDT_10   ((uint32_t)0x00000400)

◆ DMA_SxNDT_11

#define DMA_SxNDT_11   ((uint32_t)0x00000800)

◆ DMA_SxNDT_12

#define DMA_SxNDT_12   ((uint32_t)0x00001000)

◆ DMA_SxNDT_13

#define DMA_SxNDT_13   ((uint32_t)0x00002000)

◆ DMA_SxNDT_14

#define DMA_SxNDT_14   ((uint32_t)0x00004000)

◆ DMA_SxNDT_15

#define DMA_SxNDT_15   ((uint32_t)0x00008000)

◆ DMA_SxNDT_2

#define DMA_SxNDT_2   ((uint32_t)0x00000004)

◆ DMA_SxNDT_3

#define DMA_SxNDT_3   ((uint32_t)0x00000008)

◆ DMA_SxNDT_4

#define DMA_SxNDT_4   ((uint32_t)0x00000010)

◆ DMA_SxNDT_5

#define DMA_SxNDT_5   ((uint32_t)0x00000020)

◆ DMA_SxNDT_6

#define DMA_SxNDT_6   ((uint32_t)0x00000040)

◆ DMA_SxNDT_7

#define DMA_SxNDT_7   ((uint32_t)0x00000080)

◆ DMA_SxNDT_8

#define DMA_SxNDT_8   ((uint32_t)0x00000100)

◆ DMA_SxNDT_9

#define DMA_SxNDT_9   ((uint32_t)0x00000200)

◆ ETH_DMABMR_AAB

#define ETH_DMABMR_AAB   ((uint32_t)0x02000000) /* Address-Aligned beats */

◆ ETH_DMABMR_DA

#define ETH_DMABMR_DA   ((uint32_t)0x00000002) /* DMA arbitration scheme */

◆ ETH_DMABMR_DSL

#define ETH_DMABMR_DSL   ((uint32_t)0x0000007C) /* Descriptor Skip Length */

◆ ETH_DMABMR_EDE

#define ETH_DMABMR_EDE   ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */

◆ ETH_DMABMR_FB

#define ETH_DMABMR_FB   ((uint32_t)0x00010000) /* Fixed Burst */

◆ ETH_DMABMR_FPM

#define ETH_DMABMR_FPM   ((uint32_t)0x01000000) /* 4xPBL mode */

◆ ETH_DMABMR_PBL

#define ETH_DMABMR_PBL   ((uint32_t)0x00003F00) /* Programmable burst length */

◆ ETH_DMABMR_PBL_16Beat

#define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

◆ ETH_DMABMR_PBL_1Beat

#define ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */

◆ ETH_DMABMR_PBL_2Beat

#define ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */

◆ ETH_DMABMR_PBL_32Beat

#define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

◆ ETH_DMABMR_PBL_4Beat

#define ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

◆ ETH_DMABMR_PBL_4xPBL_128Beat

#define ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */

◆ ETH_DMABMR_PBL_4xPBL_16Beat

#define ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

◆ ETH_DMABMR_PBL_4xPBL_32Beat

#define ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

◆ ETH_DMABMR_PBL_4xPBL_4Beat

#define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

◆ ETH_DMABMR_PBL_4xPBL_64Beat

#define ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */

◆ ETH_DMABMR_PBL_4xPBL_8Beat

#define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

◆ ETH_DMABMR_PBL_8Beat

#define ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

◆ ETH_DMABMR_RDP

#define ETH_DMABMR_RDP   ((uint32_t)0x007E0000) /* RxDMA PBL */

◆ ETH_DMABMR_RDP_16Beat

#define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

◆ ETH_DMABMR_RDP_1Beat

#define ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */

◆ ETH_DMABMR_RDP_2Beat

#define ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */

◆ ETH_DMABMR_RDP_32Beat

#define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

◆ ETH_DMABMR_RDP_4Beat

#define ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

◆ ETH_DMABMR_RDP_4xPBL_128Beat

#define ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */

◆ ETH_DMABMR_RDP_4xPBL_16Beat

#define ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

◆ ETH_DMABMR_RDP_4xPBL_32Beat

#define ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

◆ ETH_DMABMR_RDP_4xPBL_4Beat

#define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

◆ ETH_DMABMR_RDP_4xPBL_64Beat

#define ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */

◆ ETH_DMABMR_RDP_4xPBL_8Beat

#define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

◆ ETH_DMABMR_RDP_8Beat

#define ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

◆ ETH_DMABMR_RTPR

#define ETH_DMABMR_RTPR   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */

◆ ETH_DMABMR_RTPR_1_1

#define ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000) /* Rx Tx priority ratio */

◆ ETH_DMABMR_RTPR_2_1

#define ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000) /* Rx Tx priority ratio */

◆ ETH_DMABMR_RTPR_3_1

#define ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000) /* Rx Tx priority ratio */

◆ ETH_DMABMR_RTPR_4_1

#define ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */

◆ ETH_DMABMR_SR

#define ETH_DMABMR_SR   ((uint32_t)0x00000001) /* Software reset */

◆ ETH_DMABMR_USP

#define ETH_DMABMR_USP   ((uint32_t)0x00800000) /* Use separate PBL */

◆ ETH_DMACHRBAR_HRBAP

#define ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */

◆ ETH_DMACHRDR_HRDAP

#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */

◆ ETH_DMACHTBAR_HTBAP

#define ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */

◆ ETH_DMACHTDR_HTDAP

#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */

◆ ETH_DMAIER_AISE

#define ETH_DMAIER_AISE   ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */

◆ ETH_DMAIER_ERIE

#define ETH_DMAIER_ERIE   ((uint32_t)0x00004000) /* Early receive interrupt enable */

◆ ETH_DMAIER_ETIE

#define ETH_DMAIER_ETIE   ((uint32_t)0x00000400) /* Early transmit interrupt enable */

◆ ETH_DMAIER_FBEIE

#define ETH_DMAIER_FBEIE   ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */

◆ ETH_DMAIER_NISE

#define ETH_DMAIER_NISE   ((uint32_t)0x00010000) /* Normal interrupt summary enable */

◆ ETH_DMAIER_RBUIE

#define ETH_DMAIER_RBUIE   ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */

◆ ETH_DMAIER_RIE

#define ETH_DMAIER_RIE   ((uint32_t)0x00000040) /* Receive interrupt enable */

◆ ETH_DMAIER_ROIE

#define ETH_DMAIER_ROIE   ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */

◆ ETH_DMAIER_RPSIE

#define ETH_DMAIER_RPSIE   ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */

◆ ETH_DMAIER_RWTIE

#define ETH_DMAIER_RWTIE   ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */

◆ ETH_DMAIER_TBUIE

#define ETH_DMAIER_TBUIE   ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */

◆ ETH_DMAIER_TIE

#define ETH_DMAIER_TIE   ((uint32_t)0x00000001) /* Transmit interrupt enable */

◆ ETH_DMAIER_TJTIE

#define ETH_DMAIER_TJTIE   ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */

◆ ETH_DMAIER_TPSIE

#define ETH_DMAIER_TPSIE   ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */

◆ ETH_DMAIER_TUIE

#define ETH_DMAIER_TUIE   ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */

◆ ETH_DMAMFBOCR_MFA

#define ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */

◆ ETH_DMAMFBOCR_MFC

#define ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */

◆ ETH_DMAMFBOCR_OFOC

#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */

◆ ETH_DMAMFBOCR_OMFC

#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */

◆ ETH_DMAOMR_DFRF

#define ETH_DMAOMR_DFRF   ((uint32_t)0x01000000) /* Disable flushing of received frames */

◆ ETH_DMAOMR_DTCEFD

#define ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */

◆ ETH_DMAOMR_FEF

#define ETH_DMAOMR_FEF   ((uint32_t)0x00000080) /* Forward error frames */

◆ ETH_DMAOMR_FTF

#define ETH_DMAOMR_FTF   ((uint32_t)0x00100000) /* Flush transmit FIFO */

◆ ETH_DMAOMR_FUGF

#define ETH_DMAOMR_FUGF   ((uint32_t)0x00000040) /* Forward undersized good frames */

◆ ETH_DMAOMR_OSF

#define ETH_DMAOMR_OSF   ((uint32_t)0x00000004) /* operate on second frame */

◆ ETH_DMAOMR_RSF

#define ETH_DMAOMR_RSF   ((uint32_t)0x02000000) /* Receive store and forward */

◆ ETH_DMAOMR_RTC

#define ETH_DMAOMR_RTC   ((uint32_t)0x00000018) /* receive threshold control */

◆ ETH_DMAOMR_RTC_128Bytes

#define ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */

◆ ETH_DMAOMR_RTC_32Bytes

#define ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */

◆ ETH_DMAOMR_RTC_64Bytes

#define ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */

◆ ETH_DMAOMR_RTC_96Bytes

#define ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */

◆ ETH_DMAOMR_SR

#define ETH_DMAOMR_SR   ((uint32_t)0x00000002) /* Start/stop receive */

◆ ETH_DMAOMR_ST

#define ETH_DMAOMR_ST   ((uint32_t)0x00002000) /* Start/stop transmission command */

◆ ETH_DMAOMR_TSF

#define ETH_DMAOMR_TSF   ((uint32_t)0x00200000) /* Transmit store and forward */

◆ ETH_DMAOMR_TTC

#define ETH_DMAOMR_TTC   ((uint32_t)0x0001C000) /* Transmit threshold control */

◆ ETH_DMAOMR_TTC_128Bytes

#define ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */

◆ ETH_DMAOMR_TTC_16Bytes

#define ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */

◆ ETH_DMAOMR_TTC_192Bytes

#define ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */

◆ ETH_DMAOMR_TTC_24Bytes

#define ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */

◆ ETH_DMAOMR_TTC_256Bytes

#define ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */

◆ ETH_DMAOMR_TTC_32Bytes

#define ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */

◆ ETH_DMAOMR_TTC_40Bytes

#define ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */

◆ ETH_DMAOMR_TTC_64Bytes

#define ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */

◆ ETH_DMARDLAR_SRL

#define ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF) /* Start of receive list */

◆ ETH_DMARPDR_RPD

#define ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF) /* Receive poll demand */

◆ ETH_DMASR_AIS

#define ETH_DMASR_AIS   ((uint32_t)0x00008000) /* Abnormal interrupt summary */

◆ ETH_DMASR_EBS

#define ETH_DMASR_EBS   ((uint32_t)0x03800000) /* Error bits status */

◆ ETH_DMASR_EBS_DataTransfTx

#define ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */

◆ ETH_DMASR_EBS_DescAccess

#define ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */

◆ ETH_DMASR_EBS_ReadTransf

#define ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */

◆ ETH_DMASR_ERS

#define ETH_DMASR_ERS   ((uint32_t)0x00004000) /* Early receive status */

◆ ETH_DMASR_ETS

#define ETH_DMASR_ETS   ((uint32_t)0x00000400) /* Early transmit status */

◆ ETH_DMASR_FBES

#define ETH_DMASR_FBES   ((uint32_t)0x00002000) /* Fatal bus error status */

◆ ETH_DMASR_MMCS

#define ETH_DMASR_MMCS   ((uint32_t)0x08000000) /* MMC status */

◆ ETH_DMASR_NIS

#define ETH_DMASR_NIS   ((uint32_t)0x00010000) /* Normal interrupt summary */

◆ ETH_DMASR_PMTS

#define ETH_DMASR_PMTS   ((uint32_t)0x10000000) /* PMT status */

◆ ETH_DMASR_RBUS

#define ETH_DMASR_RBUS   ((uint32_t)0x00000080) /* Receive buffer unavailable status */

◆ ETH_DMASR_ROS

#define ETH_DMASR_ROS   ((uint32_t)0x00000010) /* Receive overflow status */

◆ ETH_DMASR_RPS

#define ETH_DMASR_RPS   ((uint32_t)0x000E0000) /* Receive process state */

◆ ETH_DMASR_RPS_Closing

#define ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000) /* Running - closing descriptor */

◆ ETH_DMASR_RPS_Fetching

#define ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */

◆ ETH_DMASR_RPS_Queuing

#define ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */

◆ ETH_DMASR_RPS_Stopped

#define ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */

◆ ETH_DMASR_RPS_Suspended

#define ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */

◆ ETH_DMASR_RPS_Waiting

#define ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000) /* Running - waiting for packet */

◆ ETH_DMASR_RPSS

#define ETH_DMASR_RPSS   ((uint32_t)0x00000100) /* Receive process stopped status */

◆ ETH_DMASR_RS

#define ETH_DMASR_RS   ((uint32_t)0x00000040) /* Receive status */

◆ ETH_DMASR_RWTS

#define ETH_DMASR_RWTS   ((uint32_t)0x00000200) /* Receive watchdog timeout status */

◆ ETH_DMASR_TBUS

#define ETH_DMASR_TBUS   ((uint32_t)0x00000004) /* Transmit buffer unavailable status */

◆ ETH_DMASR_TJTS

#define ETH_DMASR_TJTS   ((uint32_t)0x00000008) /* Transmit jabber timeout status */

◆ ETH_DMASR_TPS

#define ETH_DMASR_TPS   ((uint32_t)0x00700000) /* Transmit process state */

◆ ETH_DMASR_TPS_Closing

#define ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000) /* Running - closing Rx descriptor */

◆ ETH_DMASR_TPS_Fetching

#define ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */

◆ ETH_DMASR_TPS_Reading

#define ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000) /* Running - reading the data from host memory */

◆ ETH_DMASR_TPS_Stopped

#define ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */

◆ ETH_DMASR_TPS_Suspended

#define ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */

◆ ETH_DMASR_TPS_Waiting

#define ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000) /* Running - waiting for status */

◆ ETH_DMASR_TPSS

#define ETH_DMASR_TPSS   ((uint32_t)0x00000002) /* Transmit process stopped status */

◆ ETH_DMASR_TS

#define ETH_DMASR_TS   ((uint32_t)0x00000001) /* Transmit status */

◆ ETH_DMASR_TSTS

#define ETH_DMASR_TSTS   ((uint32_t)0x20000000) /* Time-stamp trigger status */

◆ ETH_DMASR_TUS

#define ETH_DMASR_TUS   ((uint32_t)0x00000020) /* Transmit underflow status */

◆ ETH_DMATDLAR_STL

#define ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF) /* Start of transmit list */

◆ ETH_DMATPDR_TPD

#define ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */

◆ ETH_MACA0HR_MACA0H

#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF) /* MAC address0 high */

◆ ETH_MACA0LR_MACA0L

#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF) /* MAC address0 low */

◆ ETH_MACA1HR_AE

#define ETH_MACA1HR_AE   ((uint32_t)0x80000000) /* Address enable */

◆ ETH_MACA1HR_MACA1H

#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF) /* MAC address1 high */

◆ ETH_MACA1HR_MBC

#define ETH_MACA1HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

◆ ETH_MACA1HR_MBC_HBits15_8

#define ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */

◆ ETH_MACA1HR_MBC_HBits7_0

#define ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */

◆ ETH_MACA1HR_MBC_LBits15_8

#define ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */

◆ ETH_MACA1HR_MBC_LBits23_16

#define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */

◆ ETH_MACA1HR_MBC_LBits31_24

#define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */

◆ ETH_MACA1HR_MBC_LBits7_0

#define ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */

◆ ETH_MACA1HR_SA

#define ETH_MACA1HR_SA   ((uint32_t)0x40000000) /* Source address */

◆ ETH_MACA1LR_MACA1L

#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF) /* MAC address1 low */

◆ ETH_MACA2HR_AE

#define ETH_MACA2HR_AE   ((uint32_t)0x80000000) /* Address enable */

◆ ETH_MACA2HR_MACA2H

#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF) /* MAC address1 high */

◆ ETH_MACA2HR_MBC

#define ETH_MACA2HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */

◆ ETH_MACA2HR_MBC_HBits15_8

#define ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */

◆ ETH_MACA2HR_MBC_HBits7_0

#define ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */

◆ ETH_MACA2HR_MBC_LBits15_8

#define ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */

◆ ETH_MACA2HR_MBC_LBits23_16

#define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */

◆ ETH_MACA2HR_MBC_LBits31_24

#define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */

◆ ETH_MACA2HR_MBC_LBits7_0

#define ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */

◆ ETH_MACA2HR_SA

#define ETH_MACA2HR_SA   ((uint32_t)0x40000000) /* Source address */

◆ ETH_MACA2LR_MACA2L

#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF) /* MAC address2 low */

◆ ETH_MACA3HR_AE

#define ETH_MACA3HR_AE   ((uint32_t)0x80000000) /* Address enable */

◆ ETH_MACA3HR_MACA3H

#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF) /* MAC address3 high */

◆ ETH_MACA3HR_MBC

#define ETH_MACA3HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */

◆ ETH_MACA3HR_MBC_HBits15_8

#define ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */

◆ ETH_MACA3HR_MBC_HBits7_0

#define ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */

◆ ETH_MACA3HR_MBC_LBits15_8

#define ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */

◆ ETH_MACA3HR_MBC_LBits23_16

#define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */

◆ ETH_MACA3HR_MBC_LBits31_24

#define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */

◆ ETH_MACA3HR_MBC_LBits7_0

#define ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */

◆ ETH_MACA3HR_SA

#define ETH_MACA3HR_SA   ((uint32_t)0x40000000) /* Source address */

◆ ETH_MACA3LR_MACA3L

#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF) /* MAC address3 low */

◆ ETH_MACCR_APCS

#define ETH_MACCR_APCS   ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */

◆ ETH_MACCR_BL

#define ETH_MACCR_BL
Value:
((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */

◆ ETH_MACCR_BL_1

#define ETH_MACCR_BL_1   ((uint32_t)0x00000060) /* k = min (n, 1) */

◆ ETH_MACCR_BL_10

#define ETH_MACCR_BL_10   ((uint32_t)0x00000000) /* k = min (n, 10) */

◆ ETH_MACCR_BL_4

#define ETH_MACCR_BL_4   ((uint32_t)0x00000040) /* k = min (n, 4) */

◆ ETH_MACCR_BL_8

#define ETH_MACCR_BL_8   ((uint32_t)0x00000020) /* k = min (n, 8) */

◆ ETH_MACCR_CSD

#define ETH_MACCR_CSD   ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */

◆ ETH_MACCR_DC

#define ETH_MACCR_DC   ((uint32_t)0x00000010) /* Defferal check */

◆ ETH_MACCR_DM

#define ETH_MACCR_DM   ((uint32_t)0x00000800) /* Duplex mode */

◆ ETH_MACCR_FES

#define ETH_MACCR_FES   ((uint32_t)0x00004000) /* Fast ethernet speed */

◆ ETH_MACCR_IFG

#define ETH_MACCR_IFG   ((uint32_t)0x000E0000) /* Inter-frame gap */

◆ ETH_MACCR_IFG_40Bit

#define ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */

◆ ETH_MACCR_IFG_48Bit

#define ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */

◆ ETH_MACCR_IFG_56Bit

#define ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */

◆ ETH_MACCR_IFG_64Bit

#define ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */

◆ ETH_MACCR_IFG_72Bit

#define ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */

◆ ETH_MACCR_IFG_80Bit

#define ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */

◆ ETH_MACCR_IFG_88Bit

#define ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */

◆ ETH_MACCR_IFG_96Bit

#define ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */

◆ ETH_MACCR_IPCO

#define ETH_MACCR_IPCO   ((uint32_t)0x00000400) /* IP Checksum offload */

◆ ETH_MACCR_JD

#define ETH_MACCR_JD   ((uint32_t)0x00400000) /* Jabber disable */

◆ ETH_MACCR_LM

#define ETH_MACCR_LM   ((uint32_t)0x00001000) /* loopback mode */

◆ ETH_MACCR_RD

#define ETH_MACCR_RD   ((uint32_t)0x00000200) /* Retry disable */

◆ ETH_MACCR_RE

#define ETH_MACCR_RE   ((uint32_t)0x00000004) /* Receiver enable */

◆ ETH_MACCR_ROD

#define ETH_MACCR_ROD   ((uint32_t)0x00002000) /* Receive own disable */

◆ ETH_MACCR_TE

#define ETH_MACCR_TE   ((uint32_t)0x00000008) /* Transmitter enable */

◆ ETH_MACCR_WD

#define ETH_MACCR_WD   ((uint32_t)0x00800000) /* Watchdog disable */

◆ ETH_MACFCR_FCBBPA

#define ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */

◆ ETH_MACFCR_PLT

#define ETH_MACFCR_PLT   ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */

◆ ETH_MACFCR_PLT_Minus144

#define ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020) /* Pause time minus 144 slot times */

◆ ETH_MACFCR_PLT_Minus256

#define ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030) /* Pause time minus 256 slot times */

◆ ETH_MACFCR_PLT_Minus28

#define ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010) /* Pause time minus 28 slot times */

◆ ETH_MACFCR_PLT_Minus4

#define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000) /* Pause time minus 4 slot times */

◆ ETH_MACFCR_PT

#define ETH_MACFCR_PT   ((uint32_t)0xFFFF0000) /* Pause time */

◆ ETH_MACFCR_RFCE

#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004) /* Receive flow control enable */

◆ ETH_MACFCR_TFCE

#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002) /* Transmit flow control enable */

◆ ETH_MACFCR_UPFD

#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008) /* Unicast pause frame detect */

◆ ETH_MACFCR_ZQPD

#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080) /* Zero-quanta pause disable */

◆ ETH_MACFFR_BFD

#define ETH_MACFFR_BFD   ((uint32_t)0x00000020) /* Broadcast frame disable */

◆ ETH_MACFFR_DAIF

#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008) /* DA Inverse filtering */

◆ ETH_MACFFR_HM

#define ETH_MACFFR_HM   ((uint32_t)0x00000004) /* Hash multicast */

◆ ETH_MACFFR_HPF

#define ETH_MACFFR_HPF   ((uint32_t)0x00000400) /* Hash or perfect filter */

◆ ETH_MACFFR_HU

#define ETH_MACFFR_HU   ((uint32_t)0x00000002) /* Hash unicast */

◆ ETH_MACFFR_PAM

#define ETH_MACFFR_PAM   ((uint32_t)0x00000010) /* Pass all mutlicast */

◆ ETH_MACFFR_PCF

#define ETH_MACFFR_PCF   ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */

◆ ETH_MACFFR_PCF_BlockAll

#define ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */

◆ ETH_MACFFR_PCF_ForwardAll

#define ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */

◆ ETH_MACFFR_PCF_ForwardPassedAddrFilter

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */

◆ ETH_MACFFR_PM

#define ETH_MACFFR_PM   ((uint32_t)0x00000001) /* Promiscuous mode */

◆ ETH_MACFFR_RA

#define ETH_MACFFR_RA   ((uint32_t)0x80000000) /* Receive all */

◆ ETH_MACFFR_SAF

#define ETH_MACFFR_SAF   ((uint32_t)0x00000200) /* Source address filter enable */

◆ ETH_MACFFR_SAIF

#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100) /* SA inverse filtering */

◆ ETH_MACHTHR_HTH

#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF) /* Hash table high */

◆ ETH_MACHTLR_HTL

#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF) /* Hash table low */

◆ ETH_MACIMR_PMTIM

#define ETH_MACIMR_PMTIM   ((uint32_t)0x00000008) /* PMT interrupt mask */

◆ ETH_MACIMR_TSTIM

#define ETH_MACIMR_TSTIM   ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */

◆ ETH_MACMIIAR_CR

#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C) /* CR clock range: 6 cases */

◆ ETH_MACMIIAR_CR_Div102

#define ETH_MACMIIAR_CR_Div102   ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */

◆ ETH_MACMIIAR_CR_Div16

#define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */

◆ ETH_MACMIIAR_CR_Div26

#define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */

◆ ETH_MACMIIAR_CR_Div42

#define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */

◆ ETH_MACMIIAR_CR_Div62

#define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */

◆ ETH_MACMIIAR_MB

#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001) /* MII busy */

◆ ETH_MACMIIAR_MR

#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0) /* MII register in the selected PHY */

◆ ETH_MACMIIAR_MW

#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002) /* MII write */

◆ ETH_MACMIIAR_PA

#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800) /* Physical layer address */

◆ ETH_MACMIIDR_MD

#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */

◆ ETH_MACPMTCSR_GU

#define ETH_MACPMTCSR_GU   ((uint32_t)0x00000200) /* Global Unicast */

◆ ETH_MACPMTCSR_MPE

#define ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002) /* Magic Packet Enable */

◆ ETH_MACPMTCSR_MPR

#define ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020) /* Magic Packet Received */

◆ ETH_MACPMTCSR_PD

#define ETH_MACPMTCSR_PD   ((uint32_t)0x00000001) /* Power Down */

◆ ETH_MACPMTCSR_WFE

#define ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004) /* Wake-Up Frame Enable */

◆ ETH_MACPMTCSR_WFFRPR

#define ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */

◆ ETH_MACPMTCSR_WFR

#define ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040) /* Wake-Up Frame Received */

◆ ETH_MACRWUFFR_D

#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */

◆ ETH_MACSR_MMCS

#define ETH_MACSR_MMCS   ((uint32_t)0x00000010) /* MMC status */

◆ ETH_MACSR_MMCTS

#define ETH_MACSR_MMCTS   ((uint32_t)0x00000040) /* MMC transmit status */

◆ ETH_MACSR_MMMCRS

#define ETH_MACSR_MMMCRS   ((uint32_t)0x00000020) /* MMC receive status */

◆ ETH_MACSR_PMTS

#define ETH_MACSR_PMTS   ((uint32_t)0x00000008) /* PMT status */

◆ ETH_MACSR_TSTS

#define ETH_MACSR_TSTS   ((uint32_t)0x00000200) /* Time stamp trigger status */

◆ ETH_MACVLANTR_VLANTC

#define ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */

◆ ETH_MACVLANTR_VLANTI

#define ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */

◆ ETH_MMCCR_CR

#define ETH_MMCCR_CR   ((uint32_t)0x00000001) /* Counters Reset */

◆ ETH_MMCCR_CSR

#define ETH_MMCCR_CSR   ((uint32_t)0x00000002) /* Counter Stop Rollover */

◆ ETH_MMCCR_MCF

#define ETH_MMCCR_MCF   ((uint32_t)0x00000008) /* MMC Counter Freeze */

◆ ETH_MMCCR_MCFHP

#define ETH_MMCCR_MCFHP   ((uint32_t)0x00000020) /* MMC counter Full-Half preset */

◆ ETH_MMCCR_MCP

#define ETH_MMCCR_MCP   ((uint32_t)0x00000010) /* MMC counter preset */

◆ ETH_MMCCR_ROR

#define ETH_MMCCR_ROR   ((uint32_t)0x00000004) /* Reset on Read */

◆ ETH_MMCRFAECR_RFAEC

#define ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */

◆ ETH_MMCRFCECR_RFCEC

#define ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */

◆ ETH_MMCRGUFCR_RGUFC

#define ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */

◆ ETH_MMCRIMR_RFAEM

#define ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */

◆ ETH_MMCRIMR_RFCEM

#define ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */

◆ ETH_MMCRIMR_RGUFM

#define ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */

◆ ETH_MMCRIR_RFAES

#define ETH_MMCRIR_RFAES   ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */

◆ ETH_MMCRIR_RFCES

#define ETH_MMCRIR_RFCES   ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */

◆ ETH_MMCRIR_RGUFS

#define ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */

◆ ETH_MMCTGFCR_TGFC

#define ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */

◆ ETH_MMCTGFMSCCR_TGFMSCC

#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */

◆ ETH_MMCTGFSCCR_TGFSCC

#define ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */

◆ ETH_MMCTIMR_TGFM

#define ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */

◆ ETH_MMCTIMR_TGFMSCM

#define ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */

◆ ETH_MMCTIMR_TGFSCM

#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */

◆ ETH_MMCTIR_TGFMSCS

#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */

◆ ETH_MMCTIR_TGFS

#define ETH_MMCTIR_TGFS   ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */

◆ ETH_MMCTIR_TGFSCS

#define ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */

◆ ETH_PTPSSIR_STSSI

#define ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF) /* System time Sub-second increment value */

◆ ETH_PTPTSAR_TSA

#define ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF) /* Time stamp addend */

◆ ETH_PTPTSCR_TSARU

#define ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020) /* Addend register update */

◆ ETH_PTPTSCR_TSCNT

#define ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000) /* Time stamp clock node type */

◆ ETH_PTPTSCR_TSE

#define ETH_PTPTSCR_TSE   ((uint32_t)0x00000001) /* Time stamp enable */

◆ ETH_PTPTSCR_TSFCU

#define ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002) /* Time stamp fine or coarse update */

◆ ETH_PTPTSCR_TSITE

#define ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */

◆ ETH_PTPTSCR_TSSTI

#define ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004) /* Time stamp initialize */

◆ ETH_PTPTSCR_TSSTU

#define ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008) /* Time stamp update */

◆ ETH_PTPTSHR_STS

#define ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF) /* System Time second */

◆ ETH_PTPTSHUR_TSUS

#define ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */

◆ ETH_PTPTSLR_STPNS

#define ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000) /* System Time Positive or negative time */

◆ ETH_PTPTSLR_STSS

#define ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */

◆ ETH_PTPTSLUR_TSUPNS

#define ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */

◆ ETH_PTPTSLUR_TSUSS

#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */

◆ ETH_PTPTSSR_TSPTPPSV2E

#define ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */

◆ ETH_PTPTSSR_TSSARFE

#define ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */

◆ ETH_PTPTSSR_TSSEME

#define ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */

◆ ETH_PTPTSSR_TSSIPV4FE

#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */

◆ ETH_PTPTSSR_TSSIPV6FE

#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */

◆ ETH_PTPTSSR_TSSMRME

#define ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */

◆ ETH_PTPTSSR_TSSO

#define ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010) /* Time stamp seconds overflow */

◆ ETH_PTPTSSR_TSSPTPOEFE

#define ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */

◆ ETH_PTPTSSR_TSSSR

#define ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */

◆ ETH_PTPTSSR_TSTTR

#define ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020) /* Time stamp target time reached */

◆ ETH_PTPTTHR_TTSH

#define ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF) /* Target time stamp high */

◆ ETH_PTPTTLR_TTSL

#define ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF) /* Target time stamp low */

◆ EXTI_EMR_MR0

#define EXTI_EMR_MR0   ((uint32_t)0x00000001)

Event Mask on line 0

◆ EXTI_EMR_MR1

#define EXTI_EMR_MR1   ((uint32_t)0x00000002)

Event Mask on line 1

◆ EXTI_EMR_MR10

#define EXTI_EMR_MR10   ((uint32_t)0x00000400)

Event Mask on line 10

◆ EXTI_EMR_MR11

#define EXTI_EMR_MR11   ((uint32_t)0x00000800)

Event Mask on line 11

◆ EXTI_EMR_MR12

#define EXTI_EMR_MR12   ((uint32_t)0x00001000)

Event Mask on line 12

◆ EXTI_EMR_MR13

#define EXTI_EMR_MR13   ((uint32_t)0x00002000)

Event Mask on line 13

◆ EXTI_EMR_MR14

#define EXTI_EMR_MR14   ((uint32_t)0x00004000)

Event Mask on line 14

◆ EXTI_EMR_MR15

#define EXTI_EMR_MR15   ((uint32_t)0x00008000)

Event Mask on line 15

◆ EXTI_EMR_MR16

#define EXTI_EMR_MR16   ((uint32_t)0x00010000)

Event Mask on line 16

◆ EXTI_EMR_MR17

#define EXTI_EMR_MR17   ((uint32_t)0x00020000)

Event Mask on line 17

◆ EXTI_EMR_MR18

#define EXTI_EMR_MR18   ((uint32_t)0x00040000)

Event Mask on line 18

◆ EXTI_EMR_MR19

#define EXTI_EMR_MR19   ((uint32_t)0x00080000)

Event Mask on line 19

◆ EXTI_EMR_MR2

#define EXTI_EMR_MR2   ((uint32_t)0x00000004)

Event Mask on line 2

◆ EXTI_EMR_MR3

#define EXTI_EMR_MR3   ((uint32_t)0x00000008)

Event Mask on line 3

◆ EXTI_EMR_MR4

#define EXTI_EMR_MR4   ((uint32_t)0x00000010)

Event Mask on line 4

◆ EXTI_EMR_MR5

#define EXTI_EMR_MR5   ((uint32_t)0x00000020)

Event Mask on line 5

◆ EXTI_EMR_MR6

#define EXTI_EMR_MR6   ((uint32_t)0x00000040)

Event Mask on line 6

◆ EXTI_EMR_MR7

#define EXTI_EMR_MR7   ((uint32_t)0x00000080)

Event Mask on line 7

◆ EXTI_EMR_MR8

#define EXTI_EMR_MR8   ((uint32_t)0x00000100)

Event Mask on line 8

◆ EXTI_EMR_MR9

#define EXTI_EMR_MR9   ((uint32_t)0x00000200)

Event Mask on line 9

◆ EXTI_FTSR_TR0

#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

◆ EXTI_FTSR_TR1

#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

◆ EXTI_FTSR_TR10

#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

◆ EXTI_FTSR_TR11

#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

◆ EXTI_FTSR_TR12

#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

◆ EXTI_FTSR_TR13

#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

◆ EXTI_FTSR_TR14

#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

◆ EXTI_FTSR_TR15

#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

◆ EXTI_FTSR_TR16

#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

◆ EXTI_FTSR_TR17

#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

◆ EXTI_FTSR_TR18

#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

◆ EXTI_FTSR_TR19

#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)

Falling trigger event configuration bit of line 19

◆ EXTI_FTSR_TR2

#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

◆ EXTI_FTSR_TR3

#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

◆ EXTI_FTSR_TR4

#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

◆ EXTI_FTSR_TR5

#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

◆ EXTI_FTSR_TR6

#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

◆ EXTI_FTSR_TR7

#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

◆ EXTI_FTSR_TR8

#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

◆ EXTI_FTSR_TR9

#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

◆ EXTI_IMR_MR0

#define EXTI_IMR_MR0   ((uint32_t)0x00000001)

Interrupt Mask on line 0

◆ EXTI_IMR_MR1

#define EXTI_IMR_MR1   ((uint32_t)0x00000002)

Interrupt Mask on line 1

◆ EXTI_IMR_MR10

#define EXTI_IMR_MR10   ((uint32_t)0x00000400)

Interrupt Mask on line 10

◆ EXTI_IMR_MR11

#define EXTI_IMR_MR11   ((uint32_t)0x00000800)

Interrupt Mask on line 11

◆ EXTI_IMR_MR12

#define EXTI_IMR_MR12   ((uint32_t)0x00001000)

Interrupt Mask on line 12

◆ EXTI_IMR_MR13

#define EXTI_IMR_MR13   ((uint32_t)0x00002000)

Interrupt Mask on line 13

◆ EXTI_IMR_MR14

#define EXTI_IMR_MR14   ((uint32_t)0x00004000)

Interrupt Mask on line 14

◆ EXTI_IMR_MR15

#define EXTI_IMR_MR15   ((uint32_t)0x00008000)

Interrupt Mask on line 15

◆ EXTI_IMR_MR16

#define EXTI_IMR_MR16   ((uint32_t)0x00010000)

Interrupt Mask on line 16

◆ EXTI_IMR_MR17

#define EXTI_IMR_MR17   ((uint32_t)0x00020000)

Interrupt Mask on line 17

◆ EXTI_IMR_MR18

#define EXTI_IMR_MR18   ((uint32_t)0x00040000)

Interrupt Mask on line 18

◆ EXTI_IMR_MR19

#define EXTI_IMR_MR19   ((uint32_t)0x00080000)

Interrupt Mask on line 19

◆ EXTI_IMR_MR2

#define EXTI_IMR_MR2   ((uint32_t)0x00000004)

Interrupt Mask on line 2

◆ EXTI_IMR_MR3

#define EXTI_IMR_MR3   ((uint32_t)0x00000008)

Interrupt Mask on line 3

◆ EXTI_IMR_MR4

#define EXTI_IMR_MR4   ((uint32_t)0x00000010)

Interrupt Mask on line 4

◆ EXTI_IMR_MR5

#define EXTI_IMR_MR5   ((uint32_t)0x00000020)

Interrupt Mask on line 5

◆ EXTI_IMR_MR6

#define EXTI_IMR_MR6   ((uint32_t)0x00000040)

Interrupt Mask on line 6

◆ EXTI_IMR_MR7

#define EXTI_IMR_MR7   ((uint32_t)0x00000080)

Interrupt Mask on line 7

◆ EXTI_IMR_MR8

#define EXTI_IMR_MR8   ((uint32_t)0x00000100)

Interrupt Mask on line 8

◆ EXTI_IMR_MR9

#define EXTI_IMR_MR9   ((uint32_t)0x00000200)

Interrupt Mask on line 9

◆ EXTI_PR_PR0

#define EXTI_PR_PR0   ((uint32_t)0x00000001)

Pending bit for line 0

◆ EXTI_PR_PR1

#define EXTI_PR_PR1   ((uint32_t)0x00000002)

Pending bit for line 1

◆ EXTI_PR_PR10

#define EXTI_PR_PR10   ((uint32_t)0x00000400)

Pending bit for line 10

◆ EXTI_PR_PR11

#define EXTI_PR_PR11   ((uint32_t)0x00000800)

Pending bit for line 11

◆ EXTI_PR_PR12

#define EXTI_PR_PR12   ((uint32_t)0x00001000)

Pending bit for line 12

◆ EXTI_PR_PR13

#define EXTI_PR_PR13   ((uint32_t)0x00002000)

Pending bit for line 13

◆ EXTI_PR_PR14

#define EXTI_PR_PR14   ((uint32_t)0x00004000)

Pending bit for line 14

◆ EXTI_PR_PR15

#define EXTI_PR_PR15   ((uint32_t)0x00008000)

Pending bit for line 15

◆ EXTI_PR_PR16

#define EXTI_PR_PR16   ((uint32_t)0x00010000)

Pending bit for line 16

◆ EXTI_PR_PR17

#define EXTI_PR_PR17   ((uint32_t)0x00020000)

Pending bit for line 17

◆ EXTI_PR_PR18

#define EXTI_PR_PR18   ((uint32_t)0x00040000)

Pending bit for line 18

◆ EXTI_PR_PR19

#define EXTI_PR_PR19   ((uint32_t)0x00080000)

Pending bit for line 19

◆ EXTI_PR_PR2

#define EXTI_PR_PR2   ((uint32_t)0x00000004)

Pending bit for line 2

◆ EXTI_PR_PR3

#define EXTI_PR_PR3   ((uint32_t)0x00000008)

Pending bit for line 3

◆ EXTI_PR_PR4

#define EXTI_PR_PR4   ((uint32_t)0x00000010)

Pending bit for line 4

◆ EXTI_PR_PR5

#define EXTI_PR_PR5   ((uint32_t)0x00000020)

Pending bit for line 5

◆ EXTI_PR_PR6

#define EXTI_PR_PR6   ((uint32_t)0x00000040)

Pending bit for line 6

◆ EXTI_PR_PR7

#define EXTI_PR_PR7   ((uint32_t)0x00000080)

Pending bit for line 7

◆ EXTI_PR_PR8

#define EXTI_PR_PR8   ((uint32_t)0x00000100)

Pending bit for line 8

◆ EXTI_PR_PR9

#define EXTI_PR_PR9   ((uint32_t)0x00000200)

Pending bit for line 9

◆ EXTI_RTSR_TR0

#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

◆ EXTI_RTSR_TR1

#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

◆ EXTI_RTSR_TR10

#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

◆ EXTI_RTSR_TR11

#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

◆ EXTI_RTSR_TR12

#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

◆ EXTI_RTSR_TR13

#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

◆ EXTI_RTSR_TR14

#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

◆ EXTI_RTSR_TR15

#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

◆ EXTI_RTSR_TR16

#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

◆ EXTI_RTSR_TR17

#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

◆ EXTI_RTSR_TR18

#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

◆ EXTI_RTSR_TR19

#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)

Rising trigger event configuration bit of line 19

◆ EXTI_RTSR_TR2

#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

◆ EXTI_RTSR_TR3

#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

◆ EXTI_RTSR_TR4

#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

◆ EXTI_RTSR_TR5

#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

◆ EXTI_RTSR_TR6

#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

◆ EXTI_RTSR_TR7

#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

◆ EXTI_RTSR_TR8

#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

◆ EXTI_RTSR_TR9

#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

◆ EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)

Software Interrupt on line 0

◆ EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)

Software Interrupt on line 1

◆ EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)

Software Interrupt on line 10

◆ EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)

Software Interrupt on line 11

◆ EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)

Software Interrupt on line 12

◆ EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)

Software Interrupt on line 13

◆ EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)

Software Interrupt on line 14

◆ EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)

Software Interrupt on line 15

◆ EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)

Software Interrupt on line 16

◆ EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)

Software Interrupt on line 17

◆ EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)

Software Interrupt on line 18

◆ EXTI_SWIER_SWIER19

#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)

Software Interrupt on line 19

◆ EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)

Software Interrupt on line 2

◆ EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)

Software Interrupt on line 3

◆ EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)

Software Interrupt on line 4

◆ EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)

Software Interrupt on line 5

◆ EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)

Software Interrupt on line 6

◆ EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)

Software Interrupt on line 7

◆ EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)

Software Interrupt on line 8

◆ EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)

Software Interrupt on line 9

◆ FLASH_ACR_BYTE0_ADDRESS

#define FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)

◆ FLASH_ACR_BYTE2_ADDRESS

#define FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)

◆ FLASH_ACR_DCEN

#define FLASH_ACR_DCEN   ((uint32_t)0x00000400)

◆ FLASH_ACR_DCRST

#define FLASH_ACR_DCRST   ((uint32_t)0x00001000)

◆ FLASH_ACR_ICEN

#define FLASH_ACR_ICEN   ((uint32_t)0x00000200)

◆ FLASH_ACR_ICRST

#define FLASH_ACR_ICRST   ((uint32_t)0x00000800)

◆ FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY   ((uint32_t)0x00000007)

◆ FLASH_ACR_LATENCY_0WS

#define FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)

◆ FLASH_ACR_LATENCY_1WS

#define FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)

◆ FLASH_ACR_LATENCY_2WS

#define FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)

◆ FLASH_ACR_LATENCY_3WS

#define FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)

◆ FLASH_ACR_LATENCY_4WS

#define FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)

◆ FLASH_ACR_LATENCY_5WS

#define FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)

◆ FLASH_ACR_LATENCY_6WS

#define FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)

◆ FLASH_ACR_LATENCY_7WS

#define FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)

◆ FLASH_ACR_PRFTEN

#define FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)

◆ FLASH_CR_EOPIE

#define FLASH_CR_EOPIE   ((uint32_t)0x01000000)

◆ FLASH_CR_LOCK

#define FLASH_CR_LOCK   ((uint32_t)0x80000000)

◆ FLASH_CR_MER

#define FLASH_CR_MER   ((uint32_t)0x00000004)

◆ FLASH_CR_PG

#define FLASH_CR_PG   ((uint32_t)0x00000001)

◆ FLASH_CR_PSIZE_0

#define FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)

◆ FLASH_CR_PSIZE_1

#define FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)

◆ FLASH_CR_SER

#define FLASH_CR_SER   ((uint32_t)0x00000002)

◆ FLASH_CR_SNB_0

#define FLASH_CR_SNB_0   ((uint32_t)0x00000008)

◆ FLASH_CR_SNB_1

#define FLASH_CR_SNB_1   ((uint32_t)0x00000010)

◆ FLASH_CR_SNB_2

#define FLASH_CR_SNB_2   ((uint32_t)0x00000020)

◆ FLASH_CR_SNB_3

#define FLASH_CR_SNB_3   ((uint32_t)0x00000040)

◆ FLASH_CR_STRT

#define FLASH_CR_STRT   ((uint32_t)0x00010000)

◆ FLASH_OPTCR_BOR_LEV

#define FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)

◆ FLASH_OPTCR_BOR_LEV_0

#define FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)

◆ FLASH_OPTCR_BOR_LEV_1

#define FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)

◆ FLASH_OPTCR_nRST_STDBY

#define FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)

◆ FLASH_OPTCR_nRST_STOP

#define FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)

◆ FLASH_OPTCR_nWRP_0

#define FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)

◆ FLASH_OPTCR_nWRP_1

#define FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)

◆ FLASH_OPTCR_nWRP_10

#define FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)

◆ FLASH_OPTCR_nWRP_11

#define FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)

◆ FLASH_OPTCR_nWRP_2

#define FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)

◆ FLASH_OPTCR_nWRP_3

#define FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)

◆ FLASH_OPTCR_nWRP_4

#define FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)

◆ FLASH_OPTCR_nWRP_5

#define FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)

◆ FLASH_OPTCR_nWRP_6

#define FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)

◆ FLASH_OPTCR_nWRP_7

#define FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)

◆ FLASH_OPTCR_nWRP_8

#define FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)

◆ FLASH_OPTCR_nWRP_9

#define FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)

◆ FLASH_OPTCR_OPTLOCK

#define FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)

◆ FLASH_OPTCR_OPTSTRT

#define FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)

◆ FLASH_OPTCR_RDP_0

#define FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)

◆ FLASH_OPTCR_RDP_1

#define FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)

◆ FLASH_OPTCR_RDP_2

#define FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)

◆ FLASH_OPTCR_RDP_3

#define FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)

◆ FLASH_OPTCR_RDP_4

#define FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)

◆ FLASH_OPTCR_RDP_5

#define FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)

◆ FLASH_OPTCR_RDP_6

#define FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)

◆ FLASH_OPTCR_RDP_7

#define FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)

◆ FLASH_OPTCR_WDG_SW

#define FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)

◆ FLASH_SR_BSY

#define FLASH_SR_BSY   ((uint32_t)0x00010000)

◆ FLASH_SR_EOP

#define FLASH_SR_EOP   ((uint32_t)0x00000001)

◆ FLASH_SR_PGAERR

#define FLASH_SR_PGAERR   ((uint32_t)0x00000020)

◆ FLASH_SR_PGPERR

#define FLASH_SR_PGPERR   ((uint32_t)0x00000040)

◆ FLASH_SR_PGSERR

#define FLASH_SR_PGSERR   ((uint32_t)0x00000080)

◆ FLASH_SR_SOP

#define FLASH_SR_SOP   ((uint32_t)0x00000002)

◆ FLASH_SR_WRPERR

#define FLASH_SR_WRPERR   ((uint32_t)0x00000010)

◆ FSMC_BCR1_ASYNCWAIT

#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

◆ FSMC_BCR1_BURSTEN

#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

◆ FSMC_BCR1_CBURSTRW

#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

◆ FSMC_BCR1_EXTMOD

#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

◆ FSMC_BCR1_FACCEN

#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)

Flash access enable

◆ FSMC_BCR1_MBKEN

#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

◆ FSMC_BCR1_MTYP

#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR1_MTYP_0

#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)

Bit 0

◆ FSMC_BCR1_MTYP_1

#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)

Bit 1

◆ FSMC_BCR1_MUXEN

#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

◆ FSMC_BCR1_MWID

#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR1_MWID_0

#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BCR1_MWID_1

#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BCR1_WAITCFG

#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

◆ FSMC_BCR1_WAITEN

#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

◆ FSMC_BCR1_WAITPOL

#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

◆ FSMC_BCR1_WRAPMOD

#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

◆ FSMC_BCR1_WREN

#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)

Write enable bit

◆ FSMC_BCR2_ASYNCWAIT

#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

◆ FSMC_BCR2_BURSTEN

#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

◆ FSMC_BCR2_CBURSTRW

#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

◆ FSMC_BCR2_EXTMOD

#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

◆ FSMC_BCR2_FACCEN

#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)

Flash access enable

◆ FSMC_BCR2_MBKEN

#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

◆ FSMC_BCR2_MTYP

#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR2_MTYP_0

#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)

Bit 0

◆ FSMC_BCR2_MTYP_1

#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)

Bit 1

◆ FSMC_BCR2_MUXEN

#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

◆ FSMC_BCR2_MWID

#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR2_MWID_0

#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BCR2_MWID_1

#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BCR2_WAITCFG

#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

◆ FSMC_BCR2_WAITEN

#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

◆ FSMC_BCR2_WAITPOL

#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

◆ FSMC_BCR2_WRAPMOD

#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

◆ FSMC_BCR2_WREN

#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)

Write enable bit

◆ FSMC_BCR3_ASYNCWAIT

#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

◆ FSMC_BCR3_BURSTEN

#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

◆ FSMC_BCR3_CBURSTRW

#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

◆ FSMC_BCR3_EXTMOD

#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

◆ FSMC_BCR3_FACCEN

#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)

Flash access enable

◆ FSMC_BCR3_MBKEN

#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

◆ FSMC_BCR3_MTYP

#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR3_MTYP_0

#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)

Bit 0

◆ FSMC_BCR3_MTYP_1

#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)

Bit 1

◆ FSMC_BCR3_MUXEN

#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

◆ FSMC_BCR3_MWID

#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR3_MWID_0

#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BCR3_MWID_1

#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BCR3_WAITCFG

#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

◆ FSMC_BCR3_WAITEN

#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

◆ FSMC_BCR3_WAITPOL

#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit.

◆ FSMC_BCR3_WRAPMOD

#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

◆ FSMC_BCR3_WREN

#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)

Write enable bit

◆ FSMC_BCR4_ASYNCWAIT

#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

◆ FSMC_BCR4_BURSTEN

#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

◆ FSMC_BCR4_CBURSTRW

#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

◆ FSMC_BCR4_EXTMOD

#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

◆ FSMC_BCR4_FACCEN

#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)

Flash access enable

◆ FSMC_BCR4_MBKEN

#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

◆ FSMC_BCR4_MTYP

#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

◆ FSMC_BCR4_MTYP_0

#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)

Bit 0

◆ FSMC_BCR4_MTYP_1

#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)

Bit 1

◆ FSMC_BCR4_MUXEN

#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

◆ FSMC_BCR4_MWID

#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

◆ FSMC_BCR4_MWID_0

#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BCR4_MWID_1

#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BCR4_WAITCFG

#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

◆ FSMC_BCR4_WAITEN

#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

◆ FSMC_BCR4_WAITPOL

#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

◆ FSMC_BCR4_WRAPMOD

#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

◆ FSMC_BCR4_WREN

#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)

Write enable bit

◆ FSMC_BTR1_ACCMOD

#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR1_ACCMOD_0

#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BTR1_ACCMOD_1

#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BTR1_ADDHLD

#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR1_ADDHLD_0

#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BTR1_ADDHLD_1

#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BTR1_ADDHLD_2

#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BTR1_ADDHLD_3

#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BTR1_ADDSET

#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR1_ADDSET_0

#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BTR1_ADDSET_1

#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BTR1_ADDSET_2

#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BTR1_ADDSET_3

#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BTR1_BUSTURN

#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR1_BUSTURN_0

#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_BTR1_BUSTURN_1

#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_BTR1_BUSTURN_2

#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_BTR1_BUSTURN_3

#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_BTR1_CLKDIV

#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR1_CLKDIV_0

#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BTR1_CLKDIV_1

#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BTR1_CLKDIV_2

#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BTR1_CLKDIV_3

#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BTR1_DATAST

#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BTR1_DATAST_0

#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BTR1_DATAST_1

#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BTR1_DATAST_2

#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BTR1_DATAST_3

#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BTR1_DATLAT

#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR1_DATLAT_0

#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BTR1_DATLAT_1

#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BTR1_DATLAT_2

#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BTR1_DATLAT_3

#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_BTR2_ACCMOD

#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR2_ACCMOD_0

#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BTR2_ACCMOD_1

#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BTR2_ADDHLD

#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR2_ADDHLD_0

#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BTR2_ADDHLD_1

#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BTR2_ADDHLD_2

#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BTR2_ADDHLD_3

#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BTR2_ADDSET

#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR2_ADDSET_0

#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BTR2_ADDSET_1

#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BTR2_ADDSET_2

#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BTR2_ADDSET_3

#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BTR2_BUSTURN

#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR2_BUSTURN_0

#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_BTR2_BUSTURN_1

#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_BTR2_BUSTURN_2

#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_BTR2_BUSTURN_3

#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_BTR2_CLKDIV

#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR2_CLKDIV_0

#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BTR2_CLKDIV_1

#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BTR2_CLKDIV_2

#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BTR2_CLKDIV_3

#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BTR2_DATAST

#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BTR2_DATAST_0

#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BTR2_DATAST_1

#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BTR2_DATAST_2

#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BTR2_DATAST_3

#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BTR2_DATLAT

#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR2_DATLAT_0

#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BTR2_DATLAT_1

#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BTR2_DATLAT_2

#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BTR2_DATLAT_3

#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_BTR3_ACCMOD

#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR3_ACCMOD_0

#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BTR3_ACCMOD_1

#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BTR3_ADDHLD

#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR3_ADDHLD_0

#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BTR3_ADDHLD_1

#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BTR3_ADDHLD_2

#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BTR3_ADDHLD_3

#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BTR3_ADDSET

#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR3_ADDSET_0

#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BTR3_ADDSET_1

#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BTR3_ADDSET_2

#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BTR3_ADDSET_3

#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BTR3_BUSTURN

#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR3_BUSTURN_0

#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_BTR3_BUSTURN_1

#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_BTR3_BUSTURN_2

#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_BTR3_BUSTURN_3

#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_BTR3_CLKDIV

#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR3_CLKDIV_0

#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BTR3_CLKDIV_1

#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BTR3_CLKDIV_2

#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BTR3_CLKDIV_3

#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BTR3_DATAST

#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BTR3_DATAST_0

#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BTR3_DATAST_1

#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BTR3_DATAST_2

#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BTR3_DATAST_3

#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BTR3_DATLAT

#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR3_DATLAT_0

#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BTR3_DATLAT_1

#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BTR3_DATLAT_2

#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BTR3_DATLAT_3

#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_BTR4_ACCMOD

#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BTR4_ACCMOD_0

#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BTR4_ACCMOD_1

#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BTR4_ADDHLD

#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BTR4_ADDHLD_0

#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BTR4_ADDHLD_1

#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BTR4_ADDHLD_2

#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BTR4_ADDHLD_3

#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BTR4_ADDSET

#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BTR4_ADDSET_0

#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BTR4_ADDSET_1

#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BTR4_ADDSET_2

#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BTR4_ADDSET_3

#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BTR4_BUSTURN

#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

◆ FSMC_BTR4_BUSTURN_0

#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_BTR4_BUSTURN_1

#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_BTR4_BUSTURN_2

#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_BTR4_BUSTURN_3

#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_BTR4_CLKDIV

#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BTR4_CLKDIV_0

#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BTR4_CLKDIV_1

#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BTR4_CLKDIV_2

#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BTR4_CLKDIV_3

#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BTR4_DATAST

#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BTR4_DATAST_0

#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BTR4_DATAST_1

#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BTR4_DATAST_2

#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BTR4_DATAST_3

#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BTR4_DATLAT

#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BTR4_DATLAT_0

#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BTR4_DATLAT_1

#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BTR4_DATLAT_2

#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BTR4_DATLAT_3

#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_BWTR1_ACCMOD

#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR1_ACCMOD_0

#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BWTR1_ACCMOD_1

#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BWTR1_ADDHLD

#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR1_ADDHLD_0

#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BWTR1_ADDHLD_1

#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BWTR1_ADDHLD_2

#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BWTR1_ADDHLD_3

#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BWTR1_ADDSET

#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR1_ADDSET_0

#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BWTR1_ADDSET_1

#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BWTR1_ADDSET_2

#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BWTR1_ADDSET_3

#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BWTR1_CLKDIV

#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BWTR1_CLKDIV_0

#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BWTR1_CLKDIV_1

#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BWTR1_CLKDIV_2

#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BWTR1_CLKDIV_3

#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BWTR1_DATAST

#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BWTR1_DATAST_0

#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BWTR1_DATAST_1

#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BWTR1_DATAST_2

#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BWTR1_DATAST_3

#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BWTR1_DATLAT

#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BWTR1_DATLAT_0

#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BWTR1_DATLAT_1

#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BWTR1_DATLAT_2

#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BWTR1_DATLAT_3

#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_BWTR2_ACCMOD

#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR2_ACCMOD_0

#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BWTR2_ACCMOD_1

#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BWTR2_ADDHLD

#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR2_ADDHLD_0

#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BWTR2_ADDHLD_1

#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BWTR2_ADDHLD_2

#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BWTR2_ADDHLD_3

#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BWTR2_ADDSET

#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR2_ADDSET_0

#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BWTR2_ADDSET_1

#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BWTR2_ADDSET_2

#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BWTR2_ADDSET_3

#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BWTR2_CLKDIV

#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BWTR2_CLKDIV_0

#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BWTR2_CLKDIV_1

#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BWTR2_CLKDIV_2

#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BWTR2_CLKDIV_3

#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BWTR2_DATAST

#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BWTR2_DATAST_0

#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BWTR2_DATAST_1

#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BWTR2_DATAST_2

#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BWTR2_DATAST_3

#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BWTR2_DATLAT

#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BWTR2_DATLAT_0

#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BWTR2_DATLAT_1

#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BWTR2_DATLAT_2

#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BWTR2_DATLAT_3

#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_BWTR3_ACCMOD

#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR3_ACCMOD_0

#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BWTR3_ACCMOD_1

#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BWTR3_ADDHLD

#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR3_ADDHLD_0

#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BWTR3_ADDHLD_1

#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BWTR3_ADDHLD_2

#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BWTR3_ADDHLD_3

#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BWTR3_ADDSET

#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR3_ADDSET_0

#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BWTR3_ADDSET_1

#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BWTR3_ADDSET_2

#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BWTR3_ADDSET_3

#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BWTR3_CLKDIV

#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BWTR3_CLKDIV_0

#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BWTR3_CLKDIV_1

#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BWTR3_CLKDIV_2

#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BWTR3_CLKDIV_3

#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BWTR3_DATAST

#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BWTR3_DATAST_0

#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BWTR3_DATAST_1

#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BWTR3_DATAST_2

#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BWTR3_DATAST_3

#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BWTR3_DATLAT

#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BWTR3_DATLAT_0

#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BWTR3_DATLAT_1

#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BWTR3_DATLAT_2

#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BWTR3_DATLAT_3

#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_BWTR4_ACCMOD

#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

◆ FSMC_BWTR4_ACCMOD_0

#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

◆ FSMC_BWTR4_ACCMOD_1

#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

◆ FSMC_BWTR4_ADDHLD

#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

◆ FSMC_BWTR4_ADDHLD_0

#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_BWTR4_ADDHLD_1

#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_BWTR4_ADDHLD_2

#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

◆ FSMC_BWTR4_ADDHLD_3

#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

◆ FSMC_BWTR4_ADDSET

#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

◆ FSMC_BWTR4_ADDSET_0

#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_BWTR4_ADDSET_1

#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_BWTR4_ADDSET_2

#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_BWTR4_ADDSET_3

#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_BWTR4_CLKDIV

#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

◆ FSMC_BWTR4_CLKDIV_0

#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

◆ FSMC_BWTR4_CLKDIV_1

#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

◆ FSMC_BWTR4_CLKDIV_2

#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

◆ FSMC_BWTR4_CLKDIV_3

#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

◆ FSMC_BWTR4_DATAST

#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

◆ FSMC_BWTR4_DATAST_0

#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_BWTR4_DATAST_1

#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_BWTR4_DATAST_2

#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_BWTR4_DATAST_3

#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_BWTR4_DATLAT

#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

◆ FSMC_BWTR4_DATLAT_0

#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_BWTR4_DATLAT_1

#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_BWTR4_DATLAT_2

#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_BWTR4_DATLAT_3

#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_ECCR2_ECC2

#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)

ECC result

◆ FSMC_ECCR3_ECC3

#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)

ECC result

◆ FSMC_PATT2_ATTHIZ2

#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

◆ FSMC_PATT2_ATTHIZ2_0

#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_PATT2_ATTHIZ2_1

#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_PATT2_ATTHIZ2_2

#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_PATT2_ATTHIZ2_3

#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_PATT2_ATTHIZ2_4

#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)

Bit 4

◆ FSMC_PATT2_ATTHIZ2_5

#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)

Bit 5

◆ FSMC_PATT2_ATTHIZ2_6

#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)

Bit 6

◆ FSMC_PATT2_ATTHIZ2_7

#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)

Bit 7

◆ FSMC_PATT2_ATTHOLD2

#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

◆ FSMC_PATT2_ATTHOLD2_0

#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_PATT2_ATTHOLD2_1

#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_PATT2_ATTHOLD2_2

#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_PATT2_ATTHOLD2_3

#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_PATT2_ATTHOLD2_4

#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)

Bit 4

◆ FSMC_PATT2_ATTHOLD2_5

#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)

Bit 5

◆ FSMC_PATT2_ATTHOLD2_6

#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)

Bit 6

◆ FSMC_PATT2_ATTHOLD2_7

#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)

Bit 7

◆ FSMC_PATT2_ATTSET2

#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)

ATTSET2[7:0] bits (Attribute memory 2 setup time)

◆ FSMC_PATT2_ATTSET2_0

#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_PATT2_ATTSET2_1

#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_PATT2_ATTSET2_2

#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_PATT2_ATTSET2_3

#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_PATT2_ATTSET2_4

#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)

Bit 4

◆ FSMC_PATT2_ATTSET2_5

#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)

Bit 5

◆ FSMC_PATT2_ATTSET2_6

#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)

Bit 6

◆ FSMC_PATT2_ATTSET2_7

#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)

Bit 7

◆ FSMC_PATT2_ATTWAIT2

#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

◆ FSMC_PATT2_ATTWAIT2_0

#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_PATT2_ATTWAIT2_1

#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_PATT2_ATTWAIT2_2

#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_PATT2_ATTWAIT2_3

#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_PATT2_ATTWAIT2_4

#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)

Bit 4

◆ FSMC_PATT2_ATTWAIT2_5

#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)

Bit 5

◆ FSMC_PATT2_ATTWAIT2_6

#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)

Bit 6

◆ FSMC_PATT2_ATTWAIT2_7

#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)

Bit 7

◆ FSMC_PATT3_ATTHIZ3

#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

◆ FSMC_PATT3_ATTHIZ3_0

#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_PATT3_ATTHIZ3_1

#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_PATT3_ATTHIZ3_2

#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_PATT3_ATTHIZ3_3

#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_PATT3_ATTHIZ3_4

#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)

Bit 4

◆ FSMC_PATT3_ATTHIZ3_5

#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)

Bit 5

◆ FSMC_PATT3_ATTHIZ3_6

#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)

Bit 6

◆ FSMC_PATT3_ATTHIZ3_7

#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)

Bit 7

◆ FSMC_PATT3_ATTHOLD3

#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

◆ FSMC_PATT3_ATTHOLD3_0

#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_PATT3_ATTHOLD3_1

#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_PATT3_ATTHOLD3_2

#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_PATT3_ATTHOLD3_3

#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_PATT3_ATTHOLD3_4

#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)

Bit 4

◆ FSMC_PATT3_ATTHOLD3_5

#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)

Bit 5

◆ FSMC_PATT3_ATTHOLD3_6

#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)

Bit 6

◆ FSMC_PATT3_ATTHOLD3_7

#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)

Bit 7

◆ FSMC_PATT3_ATTSET3

#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)

ATTSET3[7:0] bits (Attribute memory 3 setup time)

◆ FSMC_PATT3_ATTSET3_0

#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_PATT3_ATTSET3_1

#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_PATT3_ATTSET3_2

#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_PATT3_ATTSET3_3

#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_PATT3_ATTSET3_4

#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)

Bit 4

◆ FSMC_PATT3_ATTSET3_5

#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)

Bit 5

◆ FSMC_PATT3_ATTSET3_6

#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)

Bit 6

◆ FSMC_PATT3_ATTSET3_7

#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)

Bit 7

◆ FSMC_PATT3_ATTWAIT3

#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

◆ FSMC_PATT3_ATTWAIT3_0

#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_PATT3_ATTWAIT3_1

#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_PATT3_ATTWAIT3_2

#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_PATT3_ATTWAIT3_3

#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_PATT3_ATTWAIT3_4

#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)

Bit 4

◆ FSMC_PATT3_ATTWAIT3_5

#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)

Bit 5

◆ FSMC_PATT3_ATTWAIT3_6

#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)

Bit 6

◆ FSMC_PATT3_ATTWAIT3_7

#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)

Bit 7

◆ FSMC_PATT4_ATTHIZ4

#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

◆ FSMC_PATT4_ATTHIZ4_0

#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_PATT4_ATTHIZ4_1

#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_PATT4_ATTHIZ4_2

#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_PATT4_ATTHIZ4_3

#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_PATT4_ATTHIZ4_4

#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)

Bit 4

◆ FSMC_PATT4_ATTHIZ4_5

#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)

Bit 5

◆ FSMC_PATT4_ATTHIZ4_6

#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)

Bit 6

◆ FSMC_PATT4_ATTHIZ4_7

#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)

Bit 7

◆ FSMC_PATT4_ATTHOLD4

#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

◆ FSMC_PATT4_ATTHOLD4_0

#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_PATT4_ATTHOLD4_1

#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_PATT4_ATTHOLD4_2

#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_PATT4_ATTHOLD4_3

#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_PATT4_ATTHOLD4_4

#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)

Bit 4

◆ FSMC_PATT4_ATTHOLD4_5

#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)

Bit 5

◆ FSMC_PATT4_ATTHOLD4_6

#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)

Bit 6

◆ FSMC_PATT4_ATTHOLD4_7

#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)

Bit 7

◆ FSMC_PATT4_ATTSET4

#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)

ATTSET4[7:0] bits (Attribute memory 4 setup time)

◆ FSMC_PATT4_ATTSET4_0

#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_PATT4_ATTSET4_1

#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_PATT4_ATTSET4_2

#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_PATT4_ATTSET4_3

#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_PATT4_ATTSET4_4

#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)

Bit 4

◆ FSMC_PATT4_ATTSET4_5

#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)

Bit 5

◆ FSMC_PATT4_ATTSET4_6

#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)

Bit 6

◆ FSMC_PATT4_ATTSET4_7

#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)

Bit 7

◆ FSMC_PATT4_ATTWAIT4

#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

◆ FSMC_PATT4_ATTWAIT4_0

#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_PATT4_ATTWAIT4_1

#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_PATT4_ATTWAIT4_2

#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_PATT4_ATTWAIT4_3

#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_PATT4_ATTWAIT4_4

#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)

Bit 4

◆ FSMC_PATT4_ATTWAIT4_5

#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)

Bit 5

◆ FSMC_PATT4_ATTWAIT4_6

#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)

Bit 6

◆ FSMC_PATT4_ATTWAIT4_7

#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)

Bit 7

◆ FSMC_PCR2_ECCEN

#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

◆ FSMC_PCR2_ECCPS

#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)

ECCPS[1:0] bits (ECC page size)

◆ FSMC_PCR2_ECCPS_0

#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

◆ FSMC_PCR2_ECCPS_1

#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

◆ FSMC_PCR2_ECCPS_2

#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

◆ FSMC_PCR2_PBKEN

#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

◆ FSMC_PCR2_PTYP

#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)

Memory type

◆ FSMC_PCR2_PWAITEN

#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

◆ FSMC_PCR2_PWID

#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

◆ FSMC_PCR2_PWID_0

#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_PCR2_PWID_1

#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_PCR2_TAR

#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

◆ FSMC_PCR2_TAR_0

#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)

Bit 0

◆ FSMC_PCR2_TAR_1

#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)

Bit 1

◆ FSMC_PCR2_TAR_2

#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)

Bit 2

◆ FSMC_PCR2_TAR_3

#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)

Bit 3

◆ FSMC_PCR2_TCLR

#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

◆ FSMC_PCR2_TCLR_0

#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)

Bit 0

◆ FSMC_PCR2_TCLR_1

#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)

Bit 1

◆ FSMC_PCR2_TCLR_2

#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)

Bit 2

◆ FSMC_PCR2_TCLR_3

#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)

Bit 3

◆ FSMC_PCR3_ECCEN

#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

◆ FSMC_PCR3_ECCPS

#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

◆ FSMC_PCR3_ECCPS_0

#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

◆ FSMC_PCR3_ECCPS_1

#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

◆ FSMC_PCR3_ECCPS_2

#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

◆ FSMC_PCR3_PBKEN

#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

◆ FSMC_PCR3_PTYP

#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)

Memory type

◆ FSMC_PCR3_PWAITEN

#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

◆ FSMC_PCR3_PWID

#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

◆ FSMC_PCR3_PWID_0

#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_PCR3_PWID_1

#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_PCR3_TAR

#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

◆ FSMC_PCR3_TAR_0

#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)

Bit 0

◆ FSMC_PCR3_TAR_1

#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)

Bit 1

◆ FSMC_PCR3_TAR_2

#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)

Bit 2

◆ FSMC_PCR3_TAR_3

#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)

Bit 3

◆ FSMC_PCR3_TCLR

#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

◆ FSMC_PCR3_TCLR_0

#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)

Bit 0

◆ FSMC_PCR3_TCLR_1

#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)

Bit 1

◆ FSMC_PCR3_TCLR_2

#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)

Bit 2

◆ FSMC_PCR3_TCLR_3

#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)

Bit 3

◆ FSMC_PCR4_ECCEN

#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

◆ FSMC_PCR4_ECCPS

#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

◆ FSMC_PCR4_ECCPS_0

#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

◆ FSMC_PCR4_ECCPS_1

#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

◆ FSMC_PCR4_ECCPS_2

#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

◆ FSMC_PCR4_PBKEN

#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

◆ FSMC_PCR4_PTYP

#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)

Memory type

◆ FSMC_PCR4_PWAITEN

#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

◆ FSMC_PCR4_PWID

#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

◆ FSMC_PCR4_PWID_0

#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)

Bit 0

◆ FSMC_PCR4_PWID_1

#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)

Bit 1

◆ FSMC_PCR4_TAR

#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

◆ FSMC_PCR4_TAR_0

#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)

Bit 0

◆ FSMC_PCR4_TAR_1

#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)

Bit 1

◆ FSMC_PCR4_TAR_2

#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)

Bit 2

◆ FSMC_PCR4_TAR_3

#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)

Bit 3

◆ FSMC_PCR4_TCLR

#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

◆ FSMC_PCR4_TCLR_0

#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)

Bit 0

◆ FSMC_PCR4_TCLR_1

#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)

Bit 1

◆ FSMC_PCR4_TCLR_2

#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)

Bit 2

◆ FSMC_PCR4_TCLR_3

#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)

Bit 3

◆ FSMC_PIO4_IOHIZ4

#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

◆ FSMC_PIO4_IOHIZ4_0

#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_PIO4_IOHIZ4_1

#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_PIO4_IOHIZ4_2

#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_PIO4_IOHIZ4_3

#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_PIO4_IOHIZ4_4

#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)

Bit 4

◆ FSMC_PIO4_IOHIZ4_5

#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)

Bit 5

◆ FSMC_PIO4_IOHIZ4_6

#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)

Bit 6

◆ FSMC_PIO4_IOHIZ4_7

#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)

Bit 7

◆ FSMC_PIO4_IOHOLD4

#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)

IOHOLD4[7:0] bits (I/O 4 hold time)

◆ FSMC_PIO4_IOHOLD4_0

#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_PIO4_IOHOLD4_1

#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_PIO4_IOHOLD4_2

#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_PIO4_IOHOLD4_3

#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_PIO4_IOHOLD4_4

#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)

Bit 4

◆ FSMC_PIO4_IOHOLD4_5

#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)

Bit 5

◆ FSMC_PIO4_IOHOLD4_6

#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)

Bit 6

◆ FSMC_PIO4_IOHOLD4_7

#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)

Bit 7

◆ FSMC_PIO4_IOSET4

#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)

IOSET4[7:0] bits (I/O 4 setup time)

◆ FSMC_PIO4_IOSET4_0

#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_PIO4_IOSET4_1

#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_PIO4_IOSET4_2

#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_PIO4_IOSET4_3

#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_PIO4_IOSET4_4

#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)

Bit 4

◆ FSMC_PIO4_IOSET4_5

#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)

Bit 5

◆ FSMC_PIO4_IOSET4_6

#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)

Bit 6

◆ FSMC_PIO4_IOSET4_7

#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)

Bit 7

◆ FSMC_PIO4_IOWAIT4

#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)

IOWAIT4[7:0] bits (I/O 4 wait time)

◆ FSMC_PIO4_IOWAIT4_0

#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_PIO4_IOWAIT4_1

#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_PIO4_IOWAIT4_2

#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_PIO4_IOWAIT4_3

#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_PIO4_IOWAIT4_4

#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)

Bit 4

◆ FSMC_PIO4_IOWAIT4_5

#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)

Bit 5

◆ FSMC_PIO4_IOWAIT4_6

#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)

Bit 6

◆ FSMC_PIO4_IOWAIT4_7

#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)

Bit 7

◆ FSMC_PMEM2_MEMHIZ2

#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

◆ FSMC_PMEM2_MEMHIZ2_0

#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_PMEM2_MEMHIZ2_1

#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_PMEM2_MEMHIZ2_2

#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_PMEM2_MEMHIZ2_3

#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_PMEM2_MEMHIZ2_4

#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)

Bit 4

◆ FSMC_PMEM2_MEMHIZ2_5

#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)

Bit 5

◆ FSMC_PMEM2_MEMHIZ2_6

#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)

Bit 6

◆ FSMC_PMEM2_MEMHIZ2_7

#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)

Bit 7

◆ FSMC_PMEM2_MEMHOLD2

#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)

MEMHOLD2[7:0] bits (Common memory 2 hold time)

◆ FSMC_PMEM2_MEMHOLD2_0

#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_PMEM2_MEMHOLD2_1

#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_PMEM2_MEMHOLD2_2

#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_PMEM2_MEMHOLD2_3

#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_PMEM2_MEMHOLD2_4

#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)

Bit 4

◆ FSMC_PMEM2_MEMHOLD2_5

#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)

Bit 5

◆ FSMC_PMEM2_MEMHOLD2_6

#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)

Bit 6

◆ FSMC_PMEM2_MEMHOLD2_7

#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)

Bit 7

◆ FSMC_PMEM2_MEMSET2

#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)

MEMSET2[7:0] bits (Common memory 2 setup time)

◆ FSMC_PMEM2_MEMSET2_0

#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_PMEM2_MEMSET2_1

#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_PMEM2_MEMSET2_2

#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_PMEM2_MEMSET2_3

#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_PMEM2_MEMSET2_4

#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)

Bit 4

◆ FSMC_PMEM2_MEMSET2_5

#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)

Bit 5

◆ FSMC_PMEM2_MEMSET2_6

#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)

Bit 6

◆ FSMC_PMEM2_MEMSET2_7

#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)

Bit 7

◆ FSMC_PMEM2_MEMWAIT2

#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)

MEMWAIT2[7:0] bits (Common memory 2 wait time)

◆ FSMC_PMEM2_MEMWAIT2_0

#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_PMEM2_MEMWAIT2_1

#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_PMEM2_MEMWAIT2_2

#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_PMEM2_MEMWAIT2_3

#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_PMEM2_MEMWAIT2_4

#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)

Bit 4

◆ FSMC_PMEM2_MEMWAIT2_5

#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)

Bit 5

◆ FSMC_PMEM2_MEMWAIT2_6

#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)

Bit 6

◆ FSMC_PMEM2_MEMWAIT2_7

#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)

Bit 7

◆ FSMC_PMEM3_MEMHIZ3

#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

◆ FSMC_PMEM3_MEMHIZ3_0

#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_PMEM3_MEMHIZ3_1

#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_PMEM3_MEMHIZ3_2

#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_PMEM3_MEMHIZ3_3

#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_PMEM3_MEMHIZ3_4

#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)

Bit 4

◆ FSMC_PMEM3_MEMHIZ3_5

#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)

Bit 5

◆ FSMC_PMEM3_MEMHIZ3_6

#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)

Bit 6

◆ FSMC_PMEM3_MEMHIZ3_7

#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)

Bit 7

◆ FSMC_PMEM3_MEMHOLD3

#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)

MEMHOLD3[7:0] bits (Common memory 3 hold time)

◆ FSMC_PMEM3_MEMHOLD3_0

#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_PMEM3_MEMHOLD3_1

#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_PMEM3_MEMHOLD3_2

#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_PMEM3_MEMHOLD3_3

#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_PMEM3_MEMHOLD3_4

#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)

Bit 4

◆ FSMC_PMEM3_MEMHOLD3_5

#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)

Bit 5

◆ FSMC_PMEM3_MEMHOLD3_6

#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)

Bit 6

◆ FSMC_PMEM3_MEMHOLD3_7

#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)

Bit 7

◆ FSMC_PMEM3_MEMSET3

#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)

MEMSET3[7:0] bits (Common memory 3 setup time)

◆ FSMC_PMEM3_MEMSET3_0

#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_PMEM3_MEMSET3_1

#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_PMEM3_MEMSET3_2

#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_PMEM3_MEMSET3_3

#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_PMEM3_MEMSET3_4

#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)

Bit 4

◆ FSMC_PMEM3_MEMSET3_5

#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)

Bit 5

◆ FSMC_PMEM3_MEMSET3_6

#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)

Bit 6

◆ FSMC_PMEM3_MEMSET3_7

#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)

Bit 7

◆ FSMC_PMEM3_MEMWAIT3

#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)

MEMWAIT3[7:0] bits (Common memory 3 wait time)

◆ FSMC_PMEM3_MEMWAIT3_0

#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_PMEM3_MEMWAIT3_1

#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_PMEM3_MEMWAIT3_2

#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_PMEM3_MEMWAIT3_3

#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_PMEM3_MEMWAIT3_4

#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)

Bit 4

◆ FSMC_PMEM3_MEMWAIT3_5

#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)

Bit 5

◆ FSMC_PMEM3_MEMWAIT3_6

#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)

Bit 6

◆ FSMC_PMEM3_MEMWAIT3_7

#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)

Bit 7

◆ FSMC_PMEM4_MEMHIZ4

#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

◆ FSMC_PMEM4_MEMHIZ4_0

#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)

Bit 0

◆ FSMC_PMEM4_MEMHIZ4_1

#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)

Bit 1

◆ FSMC_PMEM4_MEMHIZ4_2

#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)

Bit 2

◆ FSMC_PMEM4_MEMHIZ4_3

#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)

Bit 3

◆ FSMC_PMEM4_MEMHIZ4_4

#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)

Bit 4

◆ FSMC_PMEM4_MEMHIZ4_5

#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)

Bit 5

◆ FSMC_PMEM4_MEMHIZ4_6

#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)

Bit 6

◆ FSMC_PMEM4_MEMHIZ4_7

#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)

Bit 7

◆ FSMC_PMEM4_MEMHOLD4

#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)

MEMHOLD4[7:0] bits (Common memory 4 hold time)

◆ FSMC_PMEM4_MEMHOLD4_0

#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)

Bit 0

◆ FSMC_PMEM4_MEMHOLD4_1

#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)

Bit 1

◆ FSMC_PMEM4_MEMHOLD4_2

#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)

Bit 2

◆ FSMC_PMEM4_MEMHOLD4_3

#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)

Bit 3

◆ FSMC_PMEM4_MEMHOLD4_4

#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)

Bit 4

◆ FSMC_PMEM4_MEMHOLD4_5

#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)

Bit 5

◆ FSMC_PMEM4_MEMHOLD4_6

#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)

Bit 6

◆ FSMC_PMEM4_MEMHOLD4_7

#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)

Bit 7

◆ FSMC_PMEM4_MEMSET4

#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)

MEMSET4[7:0] bits (Common memory 4 setup time)

◆ FSMC_PMEM4_MEMSET4_0

#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)

Bit 0

◆ FSMC_PMEM4_MEMSET4_1

#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)

Bit 1

◆ FSMC_PMEM4_MEMSET4_2

#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)

Bit 2

◆ FSMC_PMEM4_MEMSET4_3

#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)

Bit 3

◆ FSMC_PMEM4_MEMSET4_4

#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)

Bit 4

◆ FSMC_PMEM4_MEMSET4_5

#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)

Bit 5

◆ FSMC_PMEM4_MEMSET4_6

#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)

Bit 6

◆ FSMC_PMEM4_MEMSET4_7

#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)

Bit 7

◆ FSMC_PMEM4_MEMWAIT4

#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)

MEMWAIT4[7:0] bits (Common memory 4 wait time)

◆ FSMC_PMEM4_MEMWAIT4_0

#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)

Bit 0

◆ FSMC_PMEM4_MEMWAIT4_1

#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)

Bit 1

◆ FSMC_PMEM4_MEMWAIT4_2

#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)

Bit 2

◆ FSMC_PMEM4_MEMWAIT4_3

#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)

Bit 3

◆ FSMC_PMEM4_MEMWAIT4_4

#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)

Bit 4

◆ FSMC_PMEM4_MEMWAIT4_5

#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)

Bit 5

◆ FSMC_PMEM4_MEMWAIT4_6

#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)

Bit 6

◆ FSMC_PMEM4_MEMWAIT4_7

#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)

Bit 7

◆ FSMC_SR2_FEMPT

#define FSMC_SR2_FEMPT   ((uint8_t)0x40)

FIFO empty

◆ FSMC_SR2_IFEN

#define FSMC_SR2_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

◆ FSMC_SR2_IFS

#define FSMC_SR2_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

◆ FSMC_SR2_ILEN

#define FSMC_SR2_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

◆ FSMC_SR2_ILS

#define FSMC_SR2_ILS   ((uint8_t)0x02)

Interrupt Level status

◆ FSMC_SR2_IREN

#define FSMC_SR2_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

◆ FSMC_SR2_IRS

#define FSMC_SR2_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

◆ FSMC_SR3_FEMPT

#define FSMC_SR3_FEMPT   ((uint8_t)0x40)

FIFO empty

◆ FSMC_SR3_IFEN

#define FSMC_SR3_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

◆ FSMC_SR3_IFS

#define FSMC_SR3_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

◆ FSMC_SR3_ILEN

#define FSMC_SR3_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

◆ FSMC_SR3_ILS

#define FSMC_SR3_ILS   ((uint8_t)0x02)

Interrupt Level status

◆ FSMC_SR3_IREN

#define FSMC_SR3_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

◆ FSMC_SR3_IRS

#define FSMC_SR3_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

◆ FSMC_SR4_FEMPT

#define FSMC_SR4_FEMPT   ((uint8_t)0x40)

FIFO empty

◆ FSMC_SR4_IFEN

#define FSMC_SR4_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

◆ FSMC_SR4_IFS

#define FSMC_SR4_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

◆ FSMC_SR4_ILEN

#define FSMC_SR4_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

◆ FSMC_SR4_ILS

#define FSMC_SR4_ILS   ((uint8_t)0x02)

Interrupt Level status

◆ FSMC_SR4_IREN

#define FSMC_SR4_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

◆ FSMC_SR4_IRS

#define FSMC_SR4_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

◆ GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_0   ((uint32_t)0x00010000)

◆ GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_1   ((uint32_t)0x00020000)

◆ GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_10   ((uint32_t)0x04000000)

◆ GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_11   ((uint32_t)0x08000000)

◆ GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_12   ((uint32_t)0x10000000)

◆ GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_13   ((uint32_t)0x20000000)

◆ GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_14   ((uint32_t)0x40000000)

◆ GPIO_BSRR_BR_15

#define GPIO_BSRR_BR_15   ((uint32_t)0x80000000)

◆ GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_2   ((uint32_t)0x00040000)

◆ GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_3   ((uint32_t)0x00080000)

◆ GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_4   ((uint32_t)0x00100000)

◆ GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_5   ((uint32_t)0x00200000)

◆ GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_6   ((uint32_t)0x00400000)

◆ GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_7   ((uint32_t)0x00800000)

◆ GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_8   ((uint32_t)0x01000000)

◆ GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_9   ((uint32_t)0x02000000)

◆ GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_0   ((uint32_t)0x00000001)

◆ GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_1   ((uint32_t)0x00000002)

◆ GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_10   ((uint32_t)0x00000400)

◆ GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_11   ((uint32_t)0x00000800)

◆ GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_12   ((uint32_t)0x00001000)

◆ GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_13   ((uint32_t)0x00002000)

◆ GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_14   ((uint32_t)0x00004000)

◆ GPIO_BSRR_BS_15

#define GPIO_BSRR_BS_15   ((uint32_t)0x00008000)

◆ GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_2   ((uint32_t)0x00000004)

◆ GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_3   ((uint32_t)0x00000008)

◆ GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_4   ((uint32_t)0x00000010)

◆ GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_5   ((uint32_t)0x00000020)

◆ GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_6   ((uint32_t)0x00000040)

◆ GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_7   ((uint32_t)0x00000080)

◆ GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_8   ((uint32_t)0x00000100)

◆ GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_9   ((uint32_t)0x00000200)

◆ GPIO_IDR_IDR_0

#define GPIO_IDR_IDR_0   ((uint32_t)0x00000001)

◆ GPIO_IDR_IDR_1

#define GPIO_IDR_IDR_1   ((uint32_t)0x00000002)

◆ GPIO_IDR_IDR_10

#define GPIO_IDR_IDR_10   ((uint32_t)0x00000400)

◆ GPIO_IDR_IDR_11

#define GPIO_IDR_IDR_11   ((uint32_t)0x00000800)

◆ GPIO_IDR_IDR_12

#define GPIO_IDR_IDR_12   ((uint32_t)0x00001000)

◆ GPIO_IDR_IDR_13

#define GPIO_IDR_IDR_13   ((uint32_t)0x00002000)

◆ GPIO_IDR_IDR_14

#define GPIO_IDR_IDR_14   ((uint32_t)0x00004000)

◆ GPIO_IDR_IDR_15

#define GPIO_IDR_IDR_15   ((uint32_t)0x00008000)

◆ GPIO_IDR_IDR_2

#define GPIO_IDR_IDR_2   ((uint32_t)0x00000004)

◆ GPIO_IDR_IDR_3

#define GPIO_IDR_IDR_3   ((uint32_t)0x00000008)

◆ GPIO_IDR_IDR_4

#define GPIO_IDR_IDR_4   ((uint32_t)0x00000010)

◆ GPIO_IDR_IDR_5

#define GPIO_IDR_IDR_5   ((uint32_t)0x00000020)

◆ GPIO_IDR_IDR_6

#define GPIO_IDR_IDR_6   ((uint32_t)0x00000040)

◆ GPIO_IDR_IDR_7

#define GPIO_IDR_IDR_7   ((uint32_t)0x00000080)

◆ GPIO_IDR_IDR_8

#define GPIO_IDR_IDR_8   ((uint32_t)0x00000100)

◆ GPIO_IDR_IDR_9

#define GPIO_IDR_IDR_9   ((uint32_t)0x00000200)

◆ GPIO_MODER_MODER0

#define GPIO_MODER_MODER0   ((uint32_t)0x00000003)

◆ GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)

◆ GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)

◆ GPIO_MODER_MODER1

#define GPIO_MODER_MODER1   ((uint32_t)0x0000000C)

◆ GPIO_MODER_MODER10

#define GPIO_MODER_MODER10   ((uint32_t)0x00300000)

◆ GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)

◆ GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)

◆ GPIO_MODER_MODER11

#define GPIO_MODER_MODER11   ((uint32_t)0x00C00000)

◆ GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)

◆ GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)

◆ GPIO_MODER_MODER12

#define GPIO_MODER_MODER12   ((uint32_t)0x03000000)

◆ GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)

◆ GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)

◆ GPIO_MODER_MODER13

#define GPIO_MODER_MODER13   ((uint32_t)0x0C000000)

◆ GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)

◆ GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)

◆ GPIO_MODER_MODER14

#define GPIO_MODER_MODER14   ((uint32_t)0x30000000)

◆ GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)

◆ GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)

◆ GPIO_MODER_MODER15

#define GPIO_MODER_MODER15   ((uint32_t)0xC0000000)

◆ GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)

◆ GPIO_MODER_MODER15_1

#define GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)

◆ GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)

◆ GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)

◆ GPIO_MODER_MODER2

#define GPIO_MODER_MODER2   ((uint32_t)0x00000030)

◆ GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)

◆ GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)

◆ GPIO_MODER_MODER3

#define GPIO_MODER_MODER3   ((uint32_t)0x000000C0)

◆ GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)

◆ GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)

◆ GPIO_MODER_MODER4

#define GPIO_MODER_MODER4   ((uint32_t)0x00000300)

◆ GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)

◆ GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)

◆ GPIO_MODER_MODER5

#define GPIO_MODER_MODER5   ((uint32_t)0x00000C00)

◆ GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)

◆ GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)

◆ GPIO_MODER_MODER6

#define GPIO_MODER_MODER6   ((uint32_t)0x00003000)

◆ GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)

◆ GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)

◆ GPIO_MODER_MODER7

#define GPIO_MODER_MODER7   ((uint32_t)0x0000C000)

◆ GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)

◆ GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)

◆ GPIO_MODER_MODER8

#define GPIO_MODER_MODER8   ((uint32_t)0x00030000)

◆ GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)

◆ GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)

◆ GPIO_MODER_MODER9

#define GPIO_MODER_MODER9   ((uint32_t)0x000C0000)

◆ GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)

◆ GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)

◆ GPIO_ODR_ODR_0

#define GPIO_ODR_ODR_0   ((uint32_t)0x00000001)

◆ GPIO_ODR_ODR_1

#define GPIO_ODR_ODR_1   ((uint32_t)0x00000002)

◆ GPIO_ODR_ODR_10

#define GPIO_ODR_ODR_10   ((uint32_t)0x00000400)

◆ GPIO_ODR_ODR_11

#define GPIO_ODR_ODR_11   ((uint32_t)0x00000800)

◆ GPIO_ODR_ODR_12

#define GPIO_ODR_ODR_12   ((uint32_t)0x00001000)

◆ GPIO_ODR_ODR_13

#define GPIO_ODR_ODR_13   ((uint32_t)0x00002000)

◆ GPIO_ODR_ODR_14

#define GPIO_ODR_ODR_14   ((uint32_t)0x00004000)

◆ GPIO_ODR_ODR_15

#define GPIO_ODR_ODR_15   ((uint32_t)0x00008000)

◆ GPIO_ODR_ODR_2

#define GPIO_ODR_ODR_2   ((uint32_t)0x00000004)

◆ GPIO_ODR_ODR_3

#define GPIO_ODR_ODR_3   ((uint32_t)0x00000008)

◆ GPIO_ODR_ODR_4

#define GPIO_ODR_ODR_4   ((uint32_t)0x00000010)

◆ GPIO_ODR_ODR_5

#define GPIO_ODR_ODR_5   ((uint32_t)0x00000020)

◆ GPIO_ODR_ODR_6

#define GPIO_ODR_ODR_6   ((uint32_t)0x00000040)

◆ GPIO_ODR_ODR_7

#define GPIO_ODR_ODR_7   ((uint32_t)0x00000080)

◆ GPIO_ODR_ODR_8

#define GPIO_ODR_ODR_8   ((uint32_t)0x00000100)

◆ GPIO_ODR_ODR_9

#define GPIO_ODR_ODR_9   ((uint32_t)0x00000200)

◆ GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)

◆ GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)

◆ GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)

◆ GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)

◆ GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)

◆ GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)

◆ GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)

◆ GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)

◆ GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)

◆ GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)

◆ GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)

◆ GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)

◆ GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)

◆ GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)

◆ GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)

◆ GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)

◆ GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)

◆ GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)

◆ GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)

◆ GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)

◆ GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)

◆ GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)

◆ GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)

◆ GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)

◆ GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)

◆ GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)

◆ GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)

◆ GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)

◆ GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)

◆ GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)

◆ GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)

◆ GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)

◆ GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)

◆ GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)

◆ GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)

◆ GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)

◆ GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)

◆ GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)

◆ GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)

◆ GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)

◆ GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)

◆ GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)

◆ GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)

◆ GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)

◆ GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)

◆ GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)

◆ GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)

◆ GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)

◆ GPIO_OTYPER_IDR_0

#define GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0

◆ GPIO_OTYPER_IDR_1

#define GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1

◆ GPIO_OTYPER_IDR_10

#define GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10

◆ GPIO_OTYPER_IDR_11

#define GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11

◆ GPIO_OTYPER_IDR_12

#define GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12

◆ GPIO_OTYPER_IDR_13

#define GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13

◆ GPIO_OTYPER_IDR_14

#define GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14

◆ GPIO_OTYPER_IDR_15

#define GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15

◆ GPIO_OTYPER_IDR_2

#define GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2

◆ GPIO_OTYPER_IDR_3

#define GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3

◆ GPIO_OTYPER_IDR_4

#define GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4

◆ GPIO_OTYPER_IDR_5

#define GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5

◆ GPIO_OTYPER_IDR_6

#define GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6

◆ GPIO_OTYPER_IDR_7

#define GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7

◆ GPIO_OTYPER_IDR_8

#define GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8

◆ GPIO_OTYPER_IDR_9

#define GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9

◆ GPIO_OTYPER_ODR_0

#define GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0

◆ GPIO_OTYPER_ODR_1

#define GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1

◆ GPIO_OTYPER_ODR_10

#define GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10

◆ GPIO_OTYPER_ODR_11

#define GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11

◆ GPIO_OTYPER_ODR_12

#define GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12

◆ GPIO_OTYPER_ODR_13

#define GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13

◆ GPIO_OTYPER_ODR_14

#define GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14

◆ GPIO_OTYPER_ODR_15

#define GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15

◆ GPIO_OTYPER_ODR_2

#define GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2

◆ GPIO_OTYPER_ODR_3

#define GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3

◆ GPIO_OTYPER_ODR_4

#define GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4

◆ GPIO_OTYPER_ODR_5

#define GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5

◆ GPIO_OTYPER_ODR_6

#define GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6

◆ GPIO_OTYPER_ODR_7

#define GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7

◆ GPIO_OTYPER_ODR_8

#define GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8

◆ GPIO_OTYPER_ODR_9

#define GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9

◆ GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)

◆ GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)

◆ GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)

◆ GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)

◆ GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)

◆ GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)

◆ GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)

◆ GPIO_OTYPER_OT_15

#define GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)

◆ GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)

◆ GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)

◆ GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)

◆ GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)

◆ GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)

◆ GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)

◆ GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)

◆ GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)

◆ GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)

◆ GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)

◆ GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)

◆ GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)

◆ GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)

◆ GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)

◆ GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)

◆ GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)

◆ GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)

◆ GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)

◆ GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)

◆ GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)

◆ GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)

◆ GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)

◆ GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)

◆ GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)

◆ GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)

◆ GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)

◆ GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)

◆ GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)

◆ GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)

◆ GPIO_PUPDR_PUPDR15_1

#define GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)

◆ GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)

◆ GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)

◆ GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)

◆ GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)

◆ GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)

◆ GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)

◆ GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)

◆ GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)

◆ GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)

◆ GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)

◆ GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)

◆ GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)

◆ GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)

◆ GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)

◆ GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)

◆ GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)

◆ GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)

◆ GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)

◆ GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)

◆ GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)

◆ GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)

◆ GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)

◆ GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)

◆ GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)

◆ GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)

◆ GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)

◆ HASH_CR_ALGO

#define HASH_CR_ALGO   ((uint32_t)0x00000080)

◆ HASH_CR_DATATYPE

#define HASH_CR_DATATYPE   ((uint32_t)0x00000030)

◆ HASH_CR_DATATYPE_0

#define HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)

◆ HASH_CR_DATATYPE_1

#define HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)

◆ HASH_CR_DINNE

#define HASH_CR_DINNE   ((uint32_t)0x00001000)

◆ HASH_CR_DMAE

#define HASH_CR_DMAE   ((uint32_t)0x00000008)

◆ HASH_CR_INIT

#define HASH_CR_INIT   ((uint32_t)0x00000004)

◆ HASH_CR_LKEY

#define HASH_CR_LKEY   ((uint32_t)0x00010000)

◆ HASH_CR_MODE

#define HASH_CR_MODE   ((uint32_t)0x00000040)

◆ HASH_CR_NBW

#define HASH_CR_NBW   ((uint32_t)0x00000F00)

◆ HASH_CR_NBW_0

#define HASH_CR_NBW_0   ((uint32_t)0x00000100)

◆ HASH_CR_NBW_1

#define HASH_CR_NBW_1   ((uint32_t)0x00000200)

◆ HASH_CR_NBW_2

#define HASH_CR_NBW_2   ((uint32_t)0x00000400)

◆ HASH_CR_NBW_3

#define HASH_CR_NBW_3   ((uint32_t)0x00000800)

◆ HASH_IMR_DCIM

#define HASH_IMR_DCIM   ((uint32_t)0x00000002)

◆ HASH_IMR_DINIM

#define HASH_IMR_DINIM   ((uint32_t)0x00000001)

◆ HASH_SR_BUSY

#define HASH_SR_BUSY   ((uint32_t)0x00000008)

◆ HASH_SR_DCIS

#define HASH_SR_DCIS   ((uint32_t)0x00000002)

◆ HASH_SR_DINIS

#define HASH_SR_DINIS   ((uint32_t)0x00000001)

◆ HASH_SR_DMAS

#define HASH_SR_DMAS   ((uint32_t)0x00000004)

◆ HASH_STR_DCAL

#define HASH_STR_DCAL   ((uint32_t)0x00000100)

◆ HASH_STR_NBW

#define HASH_STR_NBW   ((uint32_t)0x0000001F)

◆ HASH_STR_NBW_0

#define HASH_STR_NBW_0   ((uint32_t)0x00000001)

◆ HASH_STR_NBW_1

#define HASH_STR_NBW_1   ((uint32_t)0x00000002)

◆ HASH_STR_NBW_2

#define HASH_STR_NBW_2   ((uint32_t)0x00000004)

◆ HASH_STR_NBW_3

#define HASH_STR_NBW_3   ((uint32_t)0x00000008)

◆ HASH_STR_NBW_4

#define HASH_STR_NBW_4   ((uint32_t)0x00000010)

◆ I2C_CCR_CCR

#define I2C_CCR_CCR   ((uint16_t)0x0FFF)

Clock Control Register in Fast/Standard mode (Master mode)

◆ I2C_CCR_DUTY

#define I2C_CCR_DUTY   ((uint16_t)0x4000)

Fast Mode Duty Cycle

◆ I2C_CCR_FS

#define I2C_CCR_FS   ((uint16_t)0x8000)

I2C Master Mode Selection

◆ I2C_CR1_ACK

#define I2C_CR1_ACK   ((uint16_t)0x0400)

Acknowledge Enable

◆ I2C_CR1_ALERT

#define I2C_CR1_ALERT   ((uint16_t)0x2000)

SMBus Alert

◆ I2C_CR1_ENARP

#define I2C_CR1_ENARP   ((uint16_t)0x0010)

ARP Enable

◆ I2C_CR1_ENGC

#define I2C_CR1_ENGC   ((uint16_t)0x0040)

General Call Enable

◆ I2C_CR1_ENPEC

#define I2C_CR1_ENPEC   ((uint16_t)0x0020)

PEC Enable

◆ I2C_CR1_NOSTRETCH

#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)

Clock Stretching Disable (Slave mode)

◆ I2C_CR1_PE

#define I2C_CR1_PE   ((uint16_t)0x0001)

Peripheral Enable

◆ I2C_CR1_PEC

#define I2C_CR1_PEC   ((uint16_t)0x1000)

Packet Error Checking

◆ I2C_CR1_POS

#define I2C_CR1_POS   ((uint16_t)0x0800)

Acknowledge/PEC Position (for data reception)

◆ I2C_CR1_SMBTYPE

#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)

SMBus Type

◆ I2C_CR1_SMBUS

#define I2C_CR1_SMBUS   ((uint16_t)0x0002)

SMBus Mode

◆ I2C_CR1_START

#define I2C_CR1_START   ((uint16_t)0x0100)

Start Generation

◆ I2C_CR1_STOP

#define I2C_CR1_STOP   ((uint16_t)0x0200)

Stop Generation

◆ I2C_CR1_SWRST

#define I2C_CR1_SWRST   ((uint16_t)0x8000)

Software Reset

◆ I2C_CR2_DMAEN

#define I2C_CR2_DMAEN   ((uint16_t)0x0800)

DMA Requests Enable

◆ I2C_CR2_FREQ

#define I2C_CR2_FREQ   ((uint16_t)0x003F)

FREQ[5:0] bits (Peripheral Clock Frequency)

◆ I2C_CR2_FREQ_0

#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)

Bit 0

◆ I2C_CR2_FREQ_1

#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)

Bit 1

◆ I2C_CR2_FREQ_2

#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)

Bit 2

◆ I2C_CR2_FREQ_3

#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)

Bit 3

◆ I2C_CR2_FREQ_4

#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)

Bit 4

◆ I2C_CR2_FREQ_5

#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)

Bit 5

◆ I2C_CR2_ITBUFEN

#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)

Buffer Interrupt Enable

◆ I2C_CR2_ITERREN

#define I2C_CR2_ITERREN   ((uint16_t)0x0100)

Error Interrupt Enable

◆ I2C_CR2_ITEVTEN

#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)

Event Interrupt Enable

◆ I2C_CR2_LAST

#define I2C_CR2_LAST   ((uint16_t)0x1000)

DMA Last Transfer

◆ I2C_DR_DR

#define I2C_DR_DR   ((uint8_t)0xFF)

8-bit Data Register

◆ I2C_OAR1_ADD0

#define I2C_OAR1_ADD0   ((uint16_t)0x0001)

Bit 0

◆ I2C_OAR1_ADD1

#define I2C_OAR1_ADD1   ((uint16_t)0x0002)

Bit 1

◆ I2C_OAR1_ADD1_7

#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)

Interface Address

◆ I2C_OAR1_ADD2

#define I2C_OAR1_ADD2   ((uint16_t)0x0004)

Bit 2

◆ I2C_OAR1_ADD3

#define I2C_OAR1_ADD3   ((uint16_t)0x0008)

Bit 3

◆ I2C_OAR1_ADD4

#define I2C_OAR1_ADD4   ((uint16_t)0x0010)

Bit 4

◆ I2C_OAR1_ADD5

#define I2C_OAR1_ADD5   ((uint16_t)0x0020)

Bit 5

◆ I2C_OAR1_ADD6

#define I2C_OAR1_ADD6   ((uint16_t)0x0040)

Bit 6

◆ I2C_OAR1_ADD7

#define I2C_OAR1_ADD7   ((uint16_t)0x0080)

Bit 7

◆ I2C_OAR1_ADD8

#define I2C_OAR1_ADD8   ((uint16_t)0x0100)

Bit 8

◆ I2C_OAR1_ADD8_9

#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)

Interface Address

◆ I2C_OAR1_ADD9

#define I2C_OAR1_ADD9   ((uint16_t)0x0200)

Bit 9

◆ I2C_OAR1_ADDMODE

#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)

Addressing Mode (Slave mode)

◆ I2C_OAR2_ADD2

#define I2C_OAR2_ADD2   ((uint8_t)0xFE)

Interface address

◆ I2C_OAR2_ENDUAL

#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)

Dual addressing mode enable

◆ I2C_SR1_ADD10

#define I2C_SR1_ADD10   ((uint16_t)0x0008)

10-bit header sent (Master mode)

◆ I2C_SR1_ADDR

#define I2C_SR1_ADDR   ((uint16_t)0x0002)

Address sent (master mode)/matched (slave mode)

◆ I2C_SR1_AF

#define I2C_SR1_AF   ((uint16_t)0x0400)

Acknowledge Failure

◆ I2C_SR1_ARLO

#define I2C_SR1_ARLO   ((uint16_t)0x0200)

Arbitration Lost (master mode)

◆ I2C_SR1_BERR

#define I2C_SR1_BERR   ((uint16_t)0x0100)

Bus Error

◆ I2C_SR1_BTF

#define I2C_SR1_BTF   ((uint16_t)0x0004)

Byte Transfer Finished

◆ I2C_SR1_OVR

#define I2C_SR1_OVR   ((uint16_t)0x0800)

Overrun/Underrun

◆ I2C_SR1_PECERR

#define I2C_SR1_PECERR   ((uint16_t)0x1000)

PEC Error in reception

◆ I2C_SR1_RXNE

#define I2C_SR1_RXNE   ((uint16_t)0x0040)

Data Register not Empty (receivers)

◆ I2C_SR1_SB

#define I2C_SR1_SB   ((uint16_t)0x0001)

Start Bit (Master mode)

◆ I2C_SR1_SMBALERT

#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)

SMBus Alert

◆ I2C_SR1_STOPF

#define I2C_SR1_STOPF   ((uint16_t)0x0010)

Stop detection (Slave mode)

◆ I2C_SR1_TIMEOUT

#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)

Timeout or Tlow Error

◆ I2C_SR1_TXE

#define I2C_SR1_TXE   ((uint16_t)0x0080)

Data Register Empty (transmitters)

◆ I2C_SR2_BUSY

#define I2C_SR2_BUSY   ((uint16_t)0x0002)

Bus Busy

◆ I2C_SR2_DUALF

#define I2C_SR2_DUALF   ((uint16_t)0x0080)

Dual Flag (Slave mode)

◆ I2C_SR2_GENCALL

#define I2C_SR2_GENCALL   ((uint16_t)0x0010)

General Call Address (Slave mode)

◆ I2C_SR2_MSL

#define I2C_SR2_MSL   ((uint16_t)0x0001)

Master/Slave

◆ I2C_SR2_PEC

#define I2C_SR2_PEC   ((uint16_t)0xFF00)

Packet Error Checking Register

◆ I2C_SR2_SMBDEFAULT

#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)

SMBus Device Default Address (Slave mode)

◆ I2C_SR2_SMBHOST

#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)

SMBus Host Header (Slave mode)

◆ I2C_SR2_TRA

#define I2C_SR2_TRA   ((uint16_t)0x0004)

Transmitter/Receiver

◆ I2C_TRISE_TRISE

#define I2C_TRISE_TRISE   ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

◆ IWDG_KR_KEY

#define IWDG_KR_KEY   ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

◆ IWDG_PR_PR

#define IWDG_PR_PR   ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

◆ IWDG_PR_PR_0

#define IWDG_PR_PR_0   ((uint8_t)0x01)

Bit 0

◆ IWDG_PR_PR_1

#define IWDG_PR_PR_1   ((uint8_t)0x02)

Bit 1

◆ IWDG_PR_PR_2

#define IWDG_PR_PR_2   ((uint8_t)0x04)

Bit 2

◆ IWDG_RLR_RL

#define IWDG_RLR_RL   ((uint16_t)0x0FFF)

Watchdog counter reload value

◆ IWDG_SR_PVU

#define IWDG_SR_PVU   ((uint8_t)0x01)

Watchdog prescaler value update

◆ IWDG_SR_RVU

#define IWDG_SR_RVU   ((uint8_t)0x02)

Watchdog counter reload value update

◆ PWR_CR_CSBF

#define PWR_CR_CSBF   ((uint16_t)0x0008)

Clear Standby Flag

◆ PWR_CR_CWUF

#define PWR_CR_CWUF   ((uint16_t)0x0004)

Clear Wakeup Flag

◆ PWR_CR_DBP

#define PWR_CR_DBP   ((uint16_t)0x0100)

Disable Backup Domain write protection

◆ PWR_CR_FPDS

#define PWR_CR_FPDS   ((uint16_t)0x0200)

Flash power down in Stop mode

◆ PWR_CR_LPDS

#define PWR_CR_LPDS   ((uint16_t)0x0001)

Low-Power Deepsleep

◆ PWR_CR_PDDS

#define PWR_CR_PDDS   ((uint16_t)0x0002)

Power Down Deepsleep

◆ PWR_CR_PLS

#define PWR_CR_PLS   ((uint16_t)0x00E0)

PLS[2:0] bits (PVD Level Selection)

◆ PWR_CR_PLS_0

#define PWR_CR_PLS_0   ((uint16_t)0x0020)

Bit 0

◆ PWR_CR_PLS_1

#define PWR_CR_PLS_1   ((uint16_t)0x0040)

Bit 1

◆ PWR_CR_PLS_2

#define PWR_CR_PLS_2   ((uint16_t)0x0080)

Bit 2 PVD level configuration

◆ PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV0   ((uint16_t)0x0000)

PVD level 0

◆ PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV1   ((uint16_t)0x0020)

PVD level 1

◆ PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV2   ((uint16_t)0x0040)

PVD level 2

◆ PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV3   ((uint16_t)0x0060)

PVD level 3

◆ PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV4   ((uint16_t)0x0080)

PVD level 4

◆ PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)

PVD level 5

◆ PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)

PVD level 6

◆ PWR_CR_PLS_LEV7

#define PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)

PVD level 7

◆ PWR_CR_PMODE

#define PWR_CR_PMODE   PWR_CR_VOS

◆ PWR_CR_PVDE

#define PWR_CR_PVDE   ((uint16_t)0x0010)

Power Voltage Detector Enable

◆ PWR_CR_VOS

#define PWR_CR_VOS   ((uint16_t)0x4000)

Regulator voltage scaling output selection

◆ PWR_CSR_BRE

#define PWR_CSR_BRE   ((uint16_t)0x0200)

Backup regulator enable

◆ PWR_CSR_BRR

#define PWR_CSR_BRR   ((uint16_t)0x0008)

Backup regulator ready

◆ PWR_CSR_EWUP

#define PWR_CSR_EWUP   ((uint16_t)0x0100)

Enable WKUP pin

◆ PWR_CSR_PVDO

#define PWR_CSR_PVDO   ((uint16_t)0x0004)

PVD Output

◆ PWR_CSR_REGRDY

#define PWR_CSR_REGRDY   PWR_CSR_VOSRDY

◆ PWR_CSR_SBF

#define PWR_CSR_SBF   ((uint16_t)0x0002)

Standby Flag

◆ PWR_CSR_VOSRDY

#define PWR_CSR_VOSRDY   ((uint16_t)0x4000)

Regulator voltage scaling output selection ready

◆ PWR_CSR_WUF

#define PWR_CSR_WUF   ((uint16_t)0x0001)

Wakeup Flag

◆ RCC_AHB1ENR_BKPSRAMEN

#define RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)

◆ RCC_AHB1ENR_CCMDATARAMEN

#define RCC_AHB1ENR_CCMDATARAMEN   ((uint32_t)0x00100000)

◆ RCC_AHB1ENR_CRCEN

#define RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)

◆ RCC_AHB1ENR_DMA1EN

#define RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)

◆ RCC_AHB1ENR_DMA2EN

#define RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)

◆ RCC_AHB1ENR_ETHMACEN

#define RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)

◆ RCC_AHB1ENR_ETHMACPTPEN

#define RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)

◆ RCC_AHB1ENR_ETHMACRXEN

#define RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)

◆ RCC_AHB1ENR_ETHMACTXEN

#define RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)

◆ RCC_AHB1ENR_GPIOAEN

#define RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)

◆ RCC_AHB1ENR_GPIOBEN

#define RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)

◆ RCC_AHB1ENR_GPIOCEN

#define RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)

◆ RCC_AHB1ENR_GPIODEN

#define RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)

◆ RCC_AHB1ENR_GPIOEEN

#define RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)

◆ RCC_AHB1ENR_GPIOFEN

#define RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)

◆ RCC_AHB1ENR_GPIOGEN

#define RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)

◆ RCC_AHB1ENR_GPIOHEN

#define RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)

◆ RCC_AHB1ENR_GPIOIEN

#define RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)

◆ RCC_AHB1ENR_OTGHSEN

#define RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)

◆ RCC_AHB1ENR_OTGHSULPIEN

#define RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)

◆ RCC_AHB1LPENR_BKPSRAMLPEN

#define RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)

◆ RCC_AHB1LPENR_CRCLPEN

#define RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)

◆ RCC_AHB1LPENR_DMA1LPEN

#define RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)

◆ RCC_AHB1LPENR_DMA2LPEN

#define RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)

◆ RCC_AHB1LPENR_ETHMACLPEN

#define RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)

◆ RCC_AHB1LPENR_ETHMACPTPLPEN

#define RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)

◆ RCC_AHB1LPENR_ETHMACRXLPEN

#define RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)

◆ RCC_AHB1LPENR_ETHMACTXLPEN

#define RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)

◆ RCC_AHB1LPENR_FLITFLPEN

#define RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)

◆ RCC_AHB1LPENR_GPIOALPEN

#define RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)

◆ RCC_AHB1LPENR_GPIOBLPEN

#define RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)

◆ RCC_AHB1LPENR_GPIOCLPEN

#define RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)

◆ RCC_AHB1LPENR_GPIODLPEN

#define RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)

◆ RCC_AHB1LPENR_GPIOELPEN

#define RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)

◆ RCC_AHB1LPENR_GPIOFLPEN

#define RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)

◆ RCC_AHB1LPENR_GPIOGLPEN

#define RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)

◆ RCC_AHB1LPENR_GPIOHLPEN

#define RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)

◆ RCC_AHB1LPENR_GPIOILPEN

#define RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)

◆ RCC_AHB1LPENR_OTGHSLPEN

#define RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)

◆ RCC_AHB1LPENR_OTGHSULPILPEN

#define RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)

◆ RCC_AHB1LPENR_SRAM1LPEN

#define RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)

◆ RCC_AHB1LPENR_SRAM2LPEN

#define RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)

◆ RCC_AHB1RSTR_CRCRST

#define RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)

◆ RCC_AHB1RSTR_DMA1RST

#define RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)

◆ RCC_AHB1RSTR_DMA2RST

#define RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)

◆ RCC_AHB1RSTR_ETHMACRST

#define RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)

◆ RCC_AHB1RSTR_GPIOARST

#define RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)

◆ RCC_AHB1RSTR_GPIOBRST

#define RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)

◆ RCC_AHB1RSTR_GPIOCRST

#define RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)

◆ RCC_AHB1RSTR_GPIODRST

#define RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)

◆ RCC_AHB1RSTR_GPIOERST

#define RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)

◆ RCC_AHB1RSTR_GPIOFRST

#define RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)

◆ RCC_AHB1RSTR_GPIOGRST

#define RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)

◆ RCC_AHB1RSTR_GPIOHRST

#define RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)

◆ RCC_AHB1RSTR_GPIOIRST

#define RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)

◆ RCC_AHB1RSTR_OTGHRST

#define RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)

◆ RCC_AHB2ENR_CRYPEN

#define RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)

◆ RCC_AHB2ENR_DCMIEN

#define RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)

◆ RCC_AHB2ENR_HASHEN

#define RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)

◆ RCC_AHB2ENR_OTGFSEN

#define RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)

◆ RCC_AHB2ENR_RNGEN

#define RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)

◆ RCC_AHB2LPENR_CRYPLPEN

#define RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)

◆ RCC_AHB2LPENR_DCMILPEN

#define RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)

◆ RCC_AHB2LPENR_HASHLPEN

#define RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)

◆ RCC_AHB2LPENR_OTGFSLPEN

#define RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)

◆ RCC_AHB2LPENR_RNGLPEN

#define RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)

◆ RCC_AHB2RSTR_CRYPRST

#define RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)

◆ RCC_AHB2RSTR_DCMIRST

#define RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)

◆ RCC_AHB2RSTR_HSAHRST

#define RCC_AHB2RSTR_HSAHRST   ((uint32_t)0x00000020)

◆ RCC_AHB2RSTR_OTGFSRST

#define RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)

◆ RCC_AHB2RSTR_RNGRST

#define RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)

◆ RCC_AHB3ENR_FSMCEN

#define RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)

◆ RCC_AHB3LPENR_FSMCLPEN

#define RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)

◆ RCC_AHB3RSTR_FSMCRST

#define RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)

◆ RCC_APB1ENR_CAN1EN

#define RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)

◆ RCC_APB1ENR_CAN2EN

#define RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)

◆ RCC_APB1ENR_DACEN

#define RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)

◆ RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)

◆ RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)

◆ RCC_APB1ENR_I2C3EN

#define RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)

◆ RCC_APB1ENR_PWREN

#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)

◆ RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)

◆ RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)

◆ RCC_APB1ENR_TIM12EN

#define RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)

◆ RCC_APB1ENR_TIM13EN

#define RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)

◆ RCC_APB1ENR_TIM14EN

#define RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)

◆ RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)

◆ RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)

◆ RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)

◆ RCC_APB1ENR_TIM5EN

#define RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)

◆ RCC_APB1ENR_TIM6EN

#define RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)

◆ RCC_APB1ENR_TIM7EN

#define RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)

◆ RCC_APB1ENR_UART4EN

#define RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)

◆ RCC_APB1ENR_UART5EN

#define RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)

◆ RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)

◆ RCC_APB1ENR_USART3EN

#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)

◆ RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)

◆ RCC_APB1LPENR_CAN1LPEN

#define RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)

◆ RCC_APB1LPENR_CAN2LPEN

#define RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)

◆ RCC_APB1LPENR_DACLPEN

#define RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)

◆ RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)

◆ RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)

◆ RCC_APB1LPENR_I2C3LPEN

#define RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)

◆ RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)

◆ RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)

◆ RCC_APB1LPENR_SPI3LPEN

#define RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)

◆ RCC_APB1LPENR_TIM12LPEN

#define RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)

◆ RCC_APB1LPENR_TIM13LPEN

#define RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)

◆ RCC_APB1LPENR_TIM14LPEN

#define RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)

◆ RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)

◆ RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)

◆ RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)

◆ RCC_APB1LPENR_TIM5LPEN

#define RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)

◆ RCC_APB1LPENR_TIM6LPEN

#define RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)

◆ RCC_APB1LPENR_TIM7LPEN

#define RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)

◆ RCC_APB1LPENR_UART4LPEN

#define RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)

◆ RCC_APB1LPENR_UART5LPEN

#define RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)

◆ RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)

◆ RCC_APB1LPENR_USART3LPEN

#define RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)

◆ RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)

◆ RCC_APB1RSTR_CAN1RST

#define RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)

◆ RCC_APB1RSTR_CAN2RST

#define RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)

◆ RCC_APB1RSTR_DACRST

#define RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)

◆ RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)

◆ RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)

◆ RCC_APB1RSTR_I2C3RST

#define RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)

◆ RCC_APB1RSTR_PWRRST

#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)

◆ RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00008000)

◆ RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00010000)

◆ RCC_APB1RSTR_TIM12RST

#define RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)

◆ RCC_APB1RSTR_TIM13RST

#define RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)

◆ RCC_APB1RSTR_TIM14RST

#define RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)

◆ RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)

◆ RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)

◆ RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)

◆ RCC_APB1RSTR_TIM5RST

#define RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)

◆ RCC_APB1RSTR_TIM6RST

#define RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)

◆ RCC_APB1RSTR_TIM7RST

#define RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)

◆ RCC_APB1RSTR_UART4RST

#define RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)

◆ RCC_APB1RSTR_UART5RST

#define RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)

◆ RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)

◆ RCC_APB1RSTR_USART3RST

#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)

◆ RCC_APB1RSTR_WWDGEN

#define RCC_APB1RSTR_WWDGEN   ((uint32_t)0x00000800)

◆ RCC_APB2ENR_ADC1EN

#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)

◆ RCC_APB2ENR_ADC2EN

#define RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)

◆ RCC_APB2ENR_ADC3EN

#define RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)

◆ RCC_APB2ENR_SDIOEN

#define RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)

◆ RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)

◆ RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)

◆ RCC_APB2ENR_TIM10EN

#define RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)

◆ RCC_APB2ENR_TIM11EN

#define RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)

◆ RCC_APB2ENR_TIM1EN

#define RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)

◆ RCC_APB2ENR_TIM8EN

#define RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)

◆ RCC_APB2ENR_TIM9EN

#define RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)

◆ RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)

◆ RCC_APB2ENR_USART6EN

#define RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)

◆ RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)

◆ RCC_APB2LPENR_ADC2PEN

#define RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)

◆ RCC_APB2LPENR_ADC3LPEN

#define RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)

◆ RCC_APB2LPENR_SDIOLPEN

#define RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)

◆ RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)

◆ RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)

◆ RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)

◆ RCC_APB2LPENR_TIM11LPEN

#define RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)

◆ RCC_APB2LPENR_TIM1LPEN

#define RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)

◆ RCC_APB2LPENR_TIM8LPEN

#define RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)

◆ RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)

◆ RCC_APB2LPENR_USART1LPEN

#define RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)

◆ RCC_APB2LPENR_USART6LPEN

#define RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)

◆ RCC_APB2RSTR_ADCRST

#define RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)

◆ RCC_APB2RSTR_SDIORST

#define RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)

◆ RCC_APB2RSTR_SPI1

#define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST

◆ RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)

◆ RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)

◆ RCC_APB2RSTR_TIM10RST

#define RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)

◆ RCC_APB2RSTR_TIM11RST

#define RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)

◆ RCC_APB2RSTR_TIM1RST

#define RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)

◆ RCC_APB2RSTR_TIM8RST

#define RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)

◆ RCC_APB2RSTR_TIM9RST

#define RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)

◆ RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)

◆ RCC_APB2RSTR_USART6RST

#define RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST   ((uint32_t)0x00010000)

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON   ((uint32_t)0x00000001)

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY   ((uint32_t)0x00000002)

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN   ((uint32_t)0x00008000)

◆ RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)

◆ RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)

◆ RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)

HPRE[3:0] bits (AHB prescaler)

◆ RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)

Bit 0

◆ RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)

Bit 1

◆ RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)

Bit 2

◆ RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)

Bit 3

◆ RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)

SYSCLK not divided

◆ RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)

SYSCLK divided by 128

◆ RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)

SYSCLK divided by 16

◆ RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)

SYSCLK divided by 2

◆ RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)

SYSCLK divided by 256

◆ RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)

SYSCLK divided by 4

◆ RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)

SYSCLK divided by 512 PPRE1 configuration

◆ RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)

SYSCLK divided by 64

◆ RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)

SYSCLK divided by 8

◆ RCC_CFGR_I2SSRC

#define RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)

◆ RCC_CFGR_MCO1

#define RCC_CFGR_MCO1   ((uint32_t)0x00600000)

◆ RCC_CFGR_MCO1_0

#define RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)

◆ RCC_CFGR_MCO1_1

#define RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)

◆ RCC_CFGR_MCO1PRE

#define RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)

◆ RCC_CFGR_MCO1PRE_0

#define RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)

◆ RCC_CFGR_MCO1PRE_1

#define RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)

◆ RCC_CFGR_MCO1PRE_2

#define RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)

◆ RCC_CFGR_MCO2

#define RCC_CFGR_MCO2   ((uint32_t)0xC0000000)

◆ RCC_CFGR_MCO2_0

#define RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)

◆ RCC_CFGR_MCO2_1

#define RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)

◆ RCC_CFGR_MCO2PRE

#define RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)

◆ RCC_CFGR_MCO2PRE_0

#define RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)

◆ RCC_CFGR_MCO2PRE_1

#define RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)

◆ RCC_CFGR_MCO2PRE_2

#define RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)

◆ RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)

PRE1[2:0] bits (APB1 prescaler)

◆ RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)

Bit 0

◆ RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)

Bit 1

◆ RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)

Bit 2

◆ RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)

HCLK not divided

◆ RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)

HCLK divided by 16 PPRE2 configuration

◆ RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)

HCLK divided by 2

◆ RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)

HCLK divided by 4

◆ RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)

HCLK divided by 8

◆ RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)

PRE2[2:0] bits (APB2 prescaler)

◆ RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)

Bit 0

◆ RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)

Bit 1

◆ RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)

Bit 2

◆ RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)

HCLK not divided

◆ RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E000)

HCLK divided by 16 RTCPRE configuration

◆ RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)

HCLK divided by 2

◆ RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)

HCLK divided by 4

◆ RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)

HCLK divided by 8

◆ RCC_CFGR_RTCPRE

#define RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)

◆ RCC_CFGR_RTCPRE_0

#define RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)

◆ RCC_CFGR_RTCPRE_1

#define RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)

◆ RCC_CFGR_RTCPRE_2

#define RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)

◆ RCC_CFGR_RTCPRE_3

#define RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)

◆ RCC_CFGR_RTCPRE_4

#define RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)

MCO1 configuration

◆ RCC_CFGR_SW

#define RCC_CFGR_SW   ((uint32_t)0x00000003)

< SW configuration SW[1:0] bits (System clock Switch)

◆ RCC_CFGR_SW_0

#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)

Bit 0

◆ RCC_CFGR_SW_1

#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)

Bit 1

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)

HSE selected as system clock

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)

HSI selected as system clock

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)

PLL selected as system clock SWS configuration

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)

SWS[1:0] bits (System Clock Switch Status)

◆ RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)

Bit 0

◆ RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)

Bit 1

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)

HSE oscillator used as system clock

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)

HSI oscillator used as system clock

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)

PLL used as system clock HPRE configuration

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC   ((uint32_t)0x00800000)

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF   ((uint32_t)0x00000080)

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)

◆ RCC_CIR_PLLI2SRDYC

#define RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)

◆ RCC_CIR_PLLI2SRDYF

#define RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)

◆ RCC_CIR_PLLI2SRDYIE

#define RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)

◆ RCC_CR_CSSON

#define RCC_CR_CSSON   ((uint32_t)0x00080000)

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)

◆ RCC_CR_HSEON

#define RCC_CR_HSEON   ((uint32_t)0x00010000)

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY   ((uint32_t)0x00020000)

◆ RCC_CR_HSICAL

#define RCC_CR_HSICAL   ((uint32_t)0x0000FF00)

◆ RCC_CR_HSICAL_0

#define RCC_CR_HSICAL_0   ((uint32_t)0x00000100

Bit 0

◆ RCC_CR_HSICAL_1

#define RCC_CR_HSICAL_1   ((uint32_t)0x00000200

Bit 1

◆ RCC_CR_HSICAL_2

#define RCC_CR_HSICAL_2   ((uint32_t)0x00000400

Bit 2

◆ RCC_CR_HSICAL_3

#define RCC_CR_HSICAL_3   ((uint32_t)0x00000800

Bit 3

◆ RCC_CR_HSICAL_4

#define RCC_CR_HSICAL_4   ((uint32_t)0x00001000

Bit 4

◆ RCC_CR_HSICAL_5

#define RCC_CR_HSICAL_5   ((uint32_t)0x00002000

Bit 5

◆ RCC_CR_HSICAL_6

#define RCC_CR_HSICAL_6   ((uint32_t)0x00004000

Bit 6

◆ RCC_CR_HSICAL_7

#define RCC_CR_HSICAL_7   ((uint32_t)0x00008000

Bit 7

◆ RCC_CR_HSION

#define RCC_CR_HSION   ((uint32_t)0x00000001)

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)

◆ RCC_CR_HSITRIM

#define RCC_CR_HSITRIM   ((uint32_t)0x000000F8)

◆ RCC_CR_HSITRIM_0

#define RCC_CR_HSITRIM_0   ((uint32_t)0x00000008

Bit 0

◆ RCC_CR_HSITRIM_1

#define RCC_CR_HSITRIM_1   ((uint32_t)0x00000010

Bit 1

◆ RCC_CR_HSITRIM_2

#define RCC_CR_HSITRIM_2   ((uint32_t)0x00000020

Bit 2

◆ RCC_CR_HSITRIM_3

#define RCC_CR_HSITRIM_3   ((uint32_t)0x00000040

Bit 3

◆ RCC_CR_HSITRIM_4

#define RCC_CR_HSITRIM_4   ((uint32_t)0x00000080

Bit 4

◆ RCC_CR_PLLI2SON

#define RCC_CR_PLLI2SON   ((uint32_t)0x04000000)

◆ RCC_CR_PLLI2SRDY

#define RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)

◆ RCC_CR_PLLON

#define RCC_CR_PLLON   ((uint32_t)0x01000000)

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)

◆ RCC_CSR_BORRSTF

#define RCC_CSR_BORRSTF   ((uint32_t)0x02000000)

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)

◆ RCC_CSR_LSION

#define RCC_CSR_LSION   ((uint32_t)0x00000001)

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)

◆ RCC_CSR_PADRSTF

#define RCC_CSR_PADRSTF   ((uint32_t)0x04000000)

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF   ((uint32_t)0x01000000)

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)

◆ RCC_CSR_WDGRSTF

#define RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)

◆ RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)

◆ RCC_PLLCFGR_PLLM_0

#define RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)

◆ RCC_PLLCFGR_PLLM_1

#define RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)

◆ RCC_PLLCFGR_PLLM_2

#define RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)

◆ RCC_PLLCFGR_PLLM_3

#define RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)

◆ RCC_PLLCFGR_PLLM_4

#define RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)

◆ RCC_PLLCFGR_PLLM_5

#define RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)

◆ RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)

◆ RCC_PLLCFGR_PLLN_0

#define RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)

◆ RCC_PLLCFGR_PLLN_1

#define RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)

◆ RCC_PLLCFGR_PLLN_2

#define RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)

◆ RCC_PLLCFGR_PLLN_3

#define RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)

◆ RCC_PLLCFGR_PLLN_4

#define RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)

◆ RCC_PLLCFGR_PLLN_5

#define RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)

◆ RCC_PLLCFGR_PLLN_6

#define RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)

◆ RCC_PLLCFGR_PLLN_7

#define RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)

◆ RCC_PLLCFGR_PLLN_8

#define RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)

◆ RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)

◆ RCC_PLLCFGR_PLLP_0

#define RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)

◆ RCC_PLLCFGR_PLLP_1

#define RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)

◆ RCC_PLLCFGR_PLLQ

#define RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)

◆ RCC_PLLCFGR_PLLQ_0

#define RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)

◆ RCC_PLLCFGR_PLLQ_1

#define RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)

◆ RCC_PLLCFGR_PLLQ_2

#define RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)

◆ RCC_PLLCFGR_PLLQ_3

#define RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)

◆ RCC_PLLCFGR_PLLSRC

#define RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)

◆ RCC_PLLCFGR_PLLSRC_HSE

#define RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)

◆ RCC_PLLCFGR_PLLSRC_HSI

#define RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)

◆ RCC_PLLI2SCFGR_PLLI2SN

#define RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)

◆ RCC_PLLI2SCFGR_PLLI2SR

#define RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)

◆ RCC_SSCGR_INCSTEP

#define RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)

◆ RCC_SSCGR_MODPER

#define RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)

◆ RCC_SSCGR_SPREADSEL

#define RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)

◆ RCC_SSCGR_SSCGEN

#define RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)

◆ RNG_CR_IE

#define RNG_CR_IE   ((uint32_t)0x00000008)

◆ RNG_CR_RNGEN

#define RNG_CR_RNGEN   ((uint32_t)0x00000004)

◆ RNG_SR_CECS

#define RNG_SR_CECS   ((uint32_t)0x00000002)

◆ RNG_SR_CEIS

#define RNG_SR_CEIS   ((uint32_t)0x00000020)

◆ RNG_SR_DRDY

#define RNG_SR_DRDY   ((uint32_t)0x00000001)

◆ RNG_SR_SECS

#define RNG_SR_SECS   ((uint32_t)0x00000004)

◆ RNG_SR_SEIS

#define RNG_SR_SEIS   ((uint32_t)0x00000040)

◆ RTC_ALRMAR_DT

#define RTC_ALRMAR_DT   ((uint32_t)0x30000000)

◆ RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)

◆ RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)

◆ RTC_ALRMAR_DU

#define RTC_ALRMAR_DU   ((uint32_t)0x0F000000)

◆ RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)

◆ RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)

◆ RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)

◆ RTC_ALRMAR_DU_3

#define RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)

◆ RTC_ALRMAR_HT

#define RTC_ALRMAR_HT   ((uint32_t)0x00300000)

◆ RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)

◆ RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)

◆ RTC_ALRMAR_HU

#define RTC_ALRMAR_HU   ((uint32_t)0x000F0000)

◆ RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)

◆ RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)

◆ RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)

◆ RTC_ALRMAR_HU_3

#define RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)

◆ RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT   ((uint32_t)0x00007000)

◆ RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)

◆ RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)

◆ RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)

◆ RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)

◆ RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)

◆ RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)

◆ RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)

◆ RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)

◆ RTC_ALRMAR_MSK1

#define RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)

◆ RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)

◆ RTC_ALRMAR_MSK3

#define RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)

◆ RTC_ALRMAR_MSK4

#define RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)

◆ RTC_ALRMAR_PM

#define RTC_ALRMAR_PM   ((uint32_t)0x00400000)

◆ RTC_ALRMAR_ST

#define RTC_ALRMAR_ST   ((uint32_t)0x00000070)

◆ RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)

◆ RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)

◆ RTC_ALRMAR_ST_2

#define RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)

◆ RTC_ALRMAR_SU

#define RTC_ALRMAR_SU   ((uint32_t)0x0000000F)

◆ RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)

◆ RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)

◆ RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)

◆ RTC_ALRMAR_SU_3

#define RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)

◆ RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)

◆ RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)

◆ RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)

◆ RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)

◆ RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)

◆ RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)

◆ RTC_ALRMASSR_SS

#define RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)

◆ RTC_ALRMBR_DT

#define RTC_ALRMBR_DT   ((uint32_t)0x30000000)

◆ RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)

◆ RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)

◆ RTC_ALRMBR_DU

#define RTC_ALRMBR_DU   ((uint32_t)0x0F000000)

◆ RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)

◆ RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)

◆ RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)

◆ RTC_ALRMBR_DU_3

#define RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)

◆ RTC_ALRMBR_HT

#define RTC_ALRMBR_HT   ((uint32_t)0x00300000)

◆ RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)

◆ RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)

◆ RTC_ALRMBR_HU

#define RTC_ALRMBR_HU   ((uint32_t)0x000F0000)

◆ RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)

◆ RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)

◆ RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)

◆ RTC_ALRMBR_HU_3

#define RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)

◆ RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT   ((uint32_t)0x00007000)

◆ RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)

◆ RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)

◆ RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)

◆ RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)

◆ RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)

◆ RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)

◆ RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)

◆ RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)

◆ RTC_ALRMBR_MSK1

#define RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)

◆ RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)

◆ RTC_ALRMBR_MSK3

#define RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)

◆ RTC_ALRMBR_MSK4

#define RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)

◆ RTC_ALRMBR_PM

#define RTC_ALRMBR_PM   ((uint32_t)0x00400000)

◆ RTC_ALRMBR_ST

#define RTC_ALRMBR_ST   ((uint32_t)0x00000070)

◆ RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)

◆ RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)

◆ RTC_ALRMBR_ST_2

#define RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)

◆ RTC_ALRMBR_SU

#define RTC_ALRMBR_SU   ((uint32_t)0x0000000F)

◆ RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)

◆ RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)

◆ RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)

◆ RTC_ALRMBR_SU_3

#define RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)

◆ RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)

◆ RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)

◆ RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)

◆ RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)

◆ RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)

◆ RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)

◆ RTC_ALRMBSSR_SS

#define RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)

◆ RTC_BKP0R

#define RTC_BKP0R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP10R

#define RTC_BKP10R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP11R

#define RTC_BKP11R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP12R

#define RTC_BKP12R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP13R

#define RTC_BKP13R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP14R

#define RTC_BKP14R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP15R

#define RTC_BKP15R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP16R

#define RTC_BKP16R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP17R

#define RTC_BKP17R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP18R

#define RTC_BKP18R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP19R

#define RTC_BKP19R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP1R

#define RTC_BKP1R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP2R

#define RTC_BKP2R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP3R

#define RTC_BKP3R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP4R

#define RTC_BKP4R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP5R

#define RTC_BKP5R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP6R

#define RTC_BKP6R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP7R

#define RTC_BKP7R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP8R

#define RTC_BKP8R   ((uint32_t)0xFFFFFFFF)

◆ RTC_BKP9R

#define RTC_BKP9R   ((uint32_t)0xFFFFFFFF)

◆ RTC_CALIBR_DC

#define RTC_CALIBR_DC   ((uint32_t)0x0000001F)

◆ RTC_CALIBR_DCS

#define RTC_CALIBR_DCS   ((uint32_t)0x00000080)

◆ RTC_CALR_CALM

#define RTC_CALR_CALM   ((uint32_t)0x000001FF)

◆ RTC_CALR_CALM_0

#define RTC_CALR_CALM_0   ((uint32_t)0x00000001)

◆ RTC_CALR_CALM_1

#define RTC_CALR_CALM_1   ((uint32_t)0x00000002)

◆ RTC_CALR_CALM_2

#define RTC_CALR_CALM_2   ((uint32_t)0x00000004)

◆ RTC_CALR_CALM_3

#define RTC_CALR_CALM_3   ((uint32_t)0x00000008)

◆ RTC_CALR_CALM_4

#define RTC_CALR_CALM_4   ((uint32_t)0x00000010)

◆ RTC_CALR_CALM_5

#define RTC_CALR_CALM_5   ((uint32_t)0x00000020)

◆ RTC_CALR_CALM_6

#define RTC_CALR_CALM_6   ((uint32_t)0x00000040)

◆ RTC_CALR_CALM_7

#define RTC_CALR_CALM_7   ((uint32_t)0x00000080)

◆ RTC_CALR_CALM_8

#define RTC_CALR_CALM_8   ((uint32_t)0x00000100)

◆ RTC_CALR_CALP

#define RTC_CALR_CALP   ((uint32_t)0x00008000)

◆ RTC_CALR_CALW16

#define RTC_CALR_CALW16   ((uint32_t)0x00002000)

◆ RTC_CALR_CALW8

#define RTC_CALR_CALW8   ((uint32_t)0x00004000)

◆ RTC_CR_ADD1H

#define RTC_CR_ADD1H   ((uint32_t)0x00010000)

◆ RTC_CR_ALRAE

#define RTC_CR_ALRAE   ((uint32_t)0x00000100)

◆ RTC_CR_ALRAIE

#define RTC_CR_ALRAIE   ((uint32_t)0x00001000)

◆ RTC_CR_ALRBE

#define RTC_CR_ALRBE   ((uint32_t)0x00000200)

◆ RTC_CR_ALRBIE

#define RTC_CR_ALRBIE   ((uint32_t)0x00002000)

◆ RTC_CR_BCK

#define RTC_CR_BCK   ((uint32_t)0x00040000)

◆ RTC_CR_BYPSHAD

#define RTC_CR_BYPSHAD   ((uint32_t)0x00000020)

◆ RTC_CR_COE

#define RTC_CR_COE   ((uint32_t)0x00800000)

◆ RTC_CR_COSEL

#define RTC_CR_COSEL   ((uint32_t)0x00080000)

◆ RTC_CR_DCE

#define RTC_CR_DCE   ((uint32_t)0x00000080)

◆ RTC_CR_FMT

#define RTC_CR_FMT   ((uint32_t)0x00000040)

◆ RTC_CR_OSEL

#define RTC_CR_OSEL   ((uint32_t)0x00600000)

◆ RTC_CR_OSEL_0

#define RTC_CR_OSEL_0   ((uint32_t)0x00200000)

◆ RTC_CR_OSEL_1

#define RTC_CR_OSEL_1   ((uint32_t)0x00400000)

◆ RTC_CR_POL

#define RTC_CR_POL   ((uint32_t)0x00100000)

◆ RTC_CR_REFCKON

#define RTC_CR_REFCKON   ((uint32_t)0x00000010)

◆ RTC_CR_SUB1H

#define RTC_CR_SUB1H   ((uint32_t)0x00020000)

◆ RTC_CR_TSE

#define RTC_CR_TSE   ((uint32_t)0x00000800)

◆ RTC_CR_TSEDGE

#define RTC_CR_TSEDGE   ((uint32_t)0x00000008)

◆ RTC_CR_TSIE

#define RTC_CR_TSIE   ((uint32_t)0x00008000)

◆ RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL   ((uint32_t)0x00000007)

◆ RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)

◆ RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)

◆ RTC_CR_WUCKSEL_2

#define RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)

◆ RTC_CR_WUTE

#define RTC_CR_WUTE   ((uint32_t)0x00000400)

◆ RTC_CR_WUTIE

#define RTC_CR_WUTIE   ((uint32_t)0x00004000)

◆ RTC_DR_DT

#define RTC_DR_DT   ((uint32_t)0x00000030)

◆ RTC_DR_DT_0

#define RTC_DR_DT_0   ((uint32_t)0x00000010)

◆ RTC_DR_DT_1

#define RTC_DR_DT_1   ((uint32_t)0x00000020)

◆ RTC_DR_DU

#define RTC_DR_DU   ((uint32_t)0x0000000F)

◆ RTC_DR_DU_0

#define RTC_DR_DU_0   ((uint32_t)0x00000001)

◆ RTC_DR_DU_1

#define RTC_DR_DU_1   ((uint32_t)0x00000002)

◆ RTC_DR_DU_2

#define RTC_DR_DU_2   ((uint32_t)0x00000004)

◆ RTC_DR_DU_3

#define RTC_DR_DU_3   ((uint32_t)0x00000008)

◆ RTC_DR_MT

#define RTC_DR_MT   ((uint32_t)0x00001000)

◆ RTC_DR_MU

#define RTC_DR_MU   ((uint32_t)0x00000F00)

◆ RTC_DR_MU_0

#define RTC_DR_MU_0   ((uint32_t)0x00000100)

◆ RTC_DR_MU_1

#define RTC_DR_MU_1   ((uint32_t)0x00000200)

◆ RTC_DR_MU_2

#define RTC_DR_MU_2   ((uint32_t)0x00000400)

◆ RTC_DR_MU_3

#define RTC_DR_MU_3   ((uint32_t)0x00000800)

◆ RTC_DR_WDU

#define RTC_DR_WDU   ((uint32_t)0x0000E000)

◆ RTC_DR_WDU_0

#define RTC_DR_WDU_0   ((uint32_t)0x00002000)

◆ RTC_DR_WDU_1

#define RTC_DR_WDU_1   ((uint32_t)0x00004000)

◆ RTC_DR_WDU_2

#define RTC_DR_WDU_2   ((uint32_t)0x00008000)

◆ RTC_DR_YT

#define RTC_DR_YT   ((uint32_t)0x00F00000)

◆ RTC_DR_YT_0

#define RTC_DR_YT_0   ((uint32_t)0x00100000)

◆ RTC_DR_YT_1

#define RTC_DR_YT_1   ((uint32_t)0x00200000)

◆ RTC_DR_YT_2

#define RTC_DR_YT_2   ((uint32_t)0x00400000)

◆ RTC_DR_YT_3

#define RTC_DR_YT_3   ((uint32_t)0x00800000)

◆ RTC_DR_YU

#define RTC_DR_YU   ((uint32_t)0x000F0000)

◆ RTC_DR_YU_0

#define RTC_DR_YU_0   ((uint32_t)0x00010000)

◆ RTC_DR_YU_1

#define RTC_DR_YU_1   ((uint32_t)0x00020000)

◆ RTC_DR_YU_2

#define RTC_DR_YU_2   ((uint32_t)0x00040000)

◆ RTC_DR_YU_3

#define RTC_DR_YU_3   ((uint32_t)0x00080000)

◆ RTC_ISR_ALRAF

#define RTC_ISR_ALRAF   ((uint32_t)0x00000100)

◆ RTC_ISR_ALRAWF

#define RTC_ISR_ALRAWF   ((uint32_t)0x00000001)

◆ RTC_ISR_ALRBF

#define RTC_ISR_ALRBF   ((uint32_t)0x00000200)

◆ RTC_ISR_ALRBWF

#define RTC_ISR_ALRBWF   ((uint32_t)0x00000002)

◆ RTC_ISR_INIT

#define RTC_ISR_INIT   ((uint32_t)0x00000080)

◆ RTC_ISR_INITF

#define RTC_ISR_INITF   ((uint32_t)0x00000040)

◆ RTC_ISR_INITS

#define RTC_ISR_INITS   ((uint32_t)0x00000010)

◆ RTC_ISR_RECALPF

#define RTC_ISR_RECALPF   ((uint32_t)0x00010000)

◆ RTC_ISR_RSF

#define RTC_ISR_RSF   ((uint32_t)0x00000020)

◆ RTC_ISR_SHPF

#define RTC_ISR_SHPF   ((uint32_t)0x00000008)

◆ RTC_ISR_TAMP1F

#define RTC_ISR_TAMP1F   ((uint32_t)0x00002000)

◆ RTC_ISR_TSF

#define RTC_ISR_TSF   ((uint32_t)0x00000800)

◆ RTC_ISR_TSOVF

#define RTC_ISR_TSOVF   ((uint32_t)0x00001000)

◆ RTC_ISR_WUTF

#define RTC_ISR_WUTF   ((uint32_t)0x00000400)

◆ RTC_ISR_WUTWF

#define RTC_ISR_WUTWF   ((uint32_t)0x00000004)

◆ RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)

◆ RTC_PRER_PREDIV_S

#define RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)

◆ RTC_SHIFTR_ADD1S

#define RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)

◆ RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)

◆ RTC_SSR_SS

#define RTC_SSR_SS   ((uint32_t)0x0000FFFF)

◆ RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)

◆ RTC_TAFCR_TAMP1E

#define RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)

◆ RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)

◆ RTC_TAFCR_TAMPFLT

#define RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)

◆ RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)

◆ RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)

◆ RTC_TAFCR_TAMPFREQ

#define RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)

◆ RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)

◆ RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)

◆ RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)

◆ RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)

◆ RTC_TAFCR_TAMPINSEL

#define RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)

◆ RTC_TAFCR_TAMPPRCH

#define RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)

◆ RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)

◆ RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)

◆ RTC_TAFCR_TAMPPUDIS

#define RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)

◆ RTC_TAFCR_TAMPTS

#define RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)

◆ RTC_TAFCR_TSINSEL

#define RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)

◆ RTC_TR_HT

#define RTC_TR_HT   ((uint32_t)0x00300000)

◆ RTC_TR_HT_0

#define RTC_TR_HT_0   ((uint32_t)0x00100000)

◆ RTC_TR_HT_1

#define RTC_TR_HT_1   ((uint32_t)0x00200000)

◆ RTC_TR_HU

#define RTC_TR_HU   ((uint32_t)0x000F0000)

◆ RTC_TR_HU_0

#define RTC_TR_HU_0   ((uint32_t)0x00010000)

◆ RTC_TR_HU_1

#define RTC_TR_HU_1   ((uint32_t)0x00020000)

◆ RTC_TR_HU_2

#define RTC_TR_HU_2   ((uint32_t)0x00040000)

◆ RTC_TR_HU_3

#define RTC_TR_HU_3   ((uint32_t)0x00080000)

◆ RTC_TR_MNT

#define RTC_TR_MNT   ((uint32_t)0x00007000)

◆ RTC_TR_MNT_0

#define RTC_TR_MNT_0   ((uint32_t)0x00001000)

◆ RTC_TR_MNT_1

#define RTC_TR_MNT_1   ((uint32_t)0x00002000)

◆ RTC_TR_MNT_2

#define RTC_TR_MNT_2   ((uint32_t)0x00004000)

◆ RTC_TR_MNU

#define RTC_TR_MNU   ((uint32_t)0x00000F00)

◆ RTC_TR_MNU_0

#define RTC_TR_MNU_0   ((uint32_t)0x00000100)

◆ RTC_TR_MNU_1

#define RTC_TR_MNU_1   ((uint32_t)0x00000200)

◆ RTC_TR_MNU_2

#define RTC_TR_MNU_2   ((uint32_t)0x00000400)

◆ RTC_TR_MNU_3

#define RTC_TR_MNU_3   ((uint32_t)0x00000800)

◆ RTC_TR_PM

#define RTC_TR_PM   ((uint32_t)0x00400000)

◆ RTC_TR_ST

#define RTC_TR_ST   ((uint32_t)0x00000070)

◆ RTC_TR_ST_0

#define RTC_TR_ST_0   ((uint32_t)0x00000010)

◆ RTC_TR_ST_1

#define RTC_TR_ST_1   ((uint32_t)0x00000020)

◆ RTC_TR_ST_2

#define RTC_TR_ST_2   ((uint32_t)0x00000040)

◆ RTC_TR_SU

#define RTC_TR_SU   ((uint32_t)0x0000000F)

◆ RTC_TR_SU_0

#define RTC_TR_SU_0   ((uint32_t)0x00000001)

◆ RTC_TR_SU_1

#define RTC_TR_SU_1   ((uint32_t)0x00000002)

◆ RTC_TR_SU_2

#define RTC_TR_SU_2   ((uint32_t)0x00000004)

◆ RTC_TR_SU_3

#define RTC_TR_SU_3   ((uint32_t)0x00000008)

◆ RTC_TSDR_DT

#define RTC_TSDR_DT   ((uint32_t)0x00000030)

◆ RTC_TSDR_DT_0

#define RTC_TSDR_DT_0   ((uint32_t)0x00000010)

◆ RTC_TSDR_DT_1

#define RTC_TSDR_DT_1   ((uint32_t)0x00000020)

◆ RTC_TSDR_DU

#define RTC_TSDR_DU   ((uint32_t)0x0000000F)

◆ RTC_TSDR_DU_0

#define RTC_TSDR_DU_0   ((uint32_t)0x00000001)

◆ RTC_TSDR_DU_1

#define RTC_TSDR_DU_1   ((uint32_t)0x00000002)

◆ RTC_TSDR_DU_2

#define RTC_TSDR_DU_2   ((uint32_t)0x00000004)

◆ RTC_TSDR_DU_3

#define RTC_TSDR_DU_3   ((uint32_t)0x00000008)

◆ RTC_TSDR_MT

#define RTC_TSDR_MT   ((uint32_t)0x00001000)

◆ RTC_TSDR_MU

#define RTC_TSDR_MU   ((uint32_t)0x00000F00)

◆ RTC_TSDR_MU_0

#define RTC_TSDR_MU_0   ((uint32_t)0x00000100)

◆ RTC_TSDR_MU_1

#define RTC_TSDR_MU_1   ((uint32_t)0x00000200)

◆ RTC_TSDR_MU_2

#define RTC_TSDR_MU_2   ((uint32_t)0x00000400)

◆ RTC_TSDR_MU_3

#define RTC_TSDR_MU_3   ((uint32_t)0x00000800)

◆ RTC_TSDR_WDU

#define RTC_TSDR_WDU   ((uint32_t)0x0000E000)

◆ RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_0   ((uint32_t)0x00002000)

◆ RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_1   ((uint32_t)0x00004000)

◆ RTC_TSDR_WDU_2

#define RTC_TSDR_WDU_2   ((uint32_t)0x00008000)

◆ RTC_TSSSR_SS

#define RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)

◆ RTC_TSTR_HT

#define RTC_TSTR_HT   ((uint32_t)0x00300000)

◆ RTC_TSTR_HT_0

#define RTC_TSTR_HT_0   ((uint32_t)0x00100000)

◆ RTC_TSTR_HT_1

#define RTC_TSTR_HT_1   ((uint32_t)0x00200000)

◆ RTC_TSTR_HU

#define RTC_TSTR_HU   ((uint32_t)0x000F0000)

◆ RTC_TSTR_HU_0

#define RTC_TSTR_HU_0   ((uint32_t)0x00010000)

◆ RTC_TSTR_HU_1

#define RTC_TSTR_HU_1   ((uint32_t)0x00020000)

◆ RTC_TSTR_HU_2

#define RTC_TSTR_HU_2   ((uint32_t)0x00040000)

◆ RTC_TSTR_HU_3

#define RTC_TSTR_HU_3   ((uint32_t)0x00080000)

◆ RTC_TSTR_MNT

#define RTC_TSTR_MNT   ((uint32_t)0x00007000)

◆ RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_0   ((uint32_t)0x00001000)

◆ RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_1   ((uint32_t)0x00002000)

◆ RTC_TSTR_MNT_2

#define RTC_TSTR_MNT_2   ((uint32_t)0x00004000)

◆ RTC_TSTR_MNU

#define RTC_TSTR_MNU   ((uint32_t)0x00000F00)

◆ RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_0   ((uint32_t)0x00000100)

◆ RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_1   ((uint32_t)0x00000200)

◆ RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_2   ((uint32_t)0x00000400)

◆ RTC_TSTR_MNU_3

#define RTC_TSTR_MNU_3   ((uint32_t)0x00000800)

◆ RTC_TSTR_PM

#define RTC_TSTR_PM   ((uint32_t)0x00400000)

◆ RTC_TSTR_ST

#define RTC_TSTR_ST   ((uint32_t)0x00000070)

◆ RTC_TSTR_ST_0

#define RTC_TSTR_ST_0   ((uint32_t)0x00000010)

◆ RTC_TSTR_ST_1

#define RTC_TSTR_ST_1   ((uint32_t)0x00000020)

◆ RTC_TSTR_ST_2

#define RTC_TSTR_ST_2   ((uint32_t)0x00000040)

◆ RTC_TSTR_SU

#define RTC_TSTR_SU   ((uint32_t)0x0000000F)

◆ RTC_TSTR_SU_0

#define RTC_TSTR_SU_0   ((uint32_t)0x00000001)

◆ RTC_TSTR_SU_1

#define RTC_TSTR_SU_1   ((uint32_t)0x00000002)

◆ RTC_TSTR_SU_2

#define RTC_TSTR_SU_2   ((uint32_t)0x00000004)

◆ RTC_TSTR_SU_3

#define RTC_TSTR_SU_3   ((uint32_t)0x00000008)

◆ RTC_WPR_KEY

#define RTC_WPR_KEY   ((uint32_t)0x000000FF)

◆ RTC_WUTR_WUT

#define RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)

◆ SDIO_ARG_CMDARG

#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)

Command argument

◆ SDIO_CLKCR_BYPASS

#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)

Clock divider bypass enable bit

◆ SDIO_CLKCR_CLKDIV

#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)

Clock divide factor

◆ SDIO_CLKCR_CLKEN

#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)

Clock enable bit

◆ SDIO_CLKCR_HWFC_EN

#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)

HW Flow Control enable

◆ SDIO_CLKCR_NEGEDGE

#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)

SDIO_CK dephasing selection bit

◆ SDIO_CLKCR_PWRSAV

#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)

Power saving configuration bit

◆ SDIO_CLKCR_WIDBUS

#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)

WIDBUS[1:0] bits (Wide bus mode enable bit)

◆ SDIO_CLKCR_WIDBUS_0

#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)

Bit 0

◆ SDIO_CLKCR_WIDBUS_1

#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)

Bit 1

◆ SDIO_CMD_CEATACMD

#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)

CE-ATA command

◆ SDIO_CMD_CMDINDEX

#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)

Command Index

◆ SDIO_CMD_CPSMEN

#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)

Command path state machine (CPSM) Enable bit

◆ SDIO_CMD_ENCMDCOMPL

#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)

Enable CMD completion

◆ SDIO_CMD_NIEN

#define SDIO_CMD_NIEN   ((uint16_t)0x2000)

Not Interrupt Enable

◆ SDIO_CMD_SDIOSUSPEND

#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)

SD I/O suspend command

◆ SDIO_CMD_WAITINT

#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)

CPSM Waits for Interrupt Request

◆ SDIO_CMD_WAITPEND

#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)

CPSM Waits for ends of data transfer (CmdPend internal signal)

◆ SDIO_CMD_WAITRESP

#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)

WAITRESP[1:0] bits (Wait for response bits)

◆ SDIO_CMD_WAITRESP_0

#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)

Bit 0

◆ SDIO_CMD_WAITRESP_1

#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)

Bit 1

◆ SDIO_DCOUNT_DATACOUNT

#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)

Data count value

◆ SDIO_DCTRL_DBLOCKSIZE

#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)

DBLOCKSIZE[3:0] bits (Data block size)

◆ SDIO_DCTRL_DBLOCKSIZE_0

#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)

Bit 0

◆ SDIO_DCTRL_DBLOCKSIZE_1

#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)

Bit 1

◆ SDIO_DCTRL_DBLOCKSIZE_2

#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)

Bit 2

◆ SDIO_DCTRL_DBLOCKSIZE_3

#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)

Bit 3

◆ SDIO_DCTRL_DMAEN

#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)

DMA enabled bit

◆ SDIO_DCTRL_DTDIR

#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)

Data transfer direction selection

◆ SDIO_DCTRL_DTEN

#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)

Data transfer enabled bit

◆ SDIO_DCTRL_DTMODE

#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)

Data transfer mode selection

◆ SDIO_DCTRL_RWMOD

#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)

Read wait mode

◆ SDIO_DCTRL_RWSTART

#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)

Read wait start

◆ SDIO_DCTRL_RWSTOP

#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)

Read wait stop

◆ SDIO_DCTRL_SDIOEN

#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)

SD I/O enable functions

◆ SDIO_DLEN_DATALENGTH

#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)

Data length value

◆ SDIO_DTIMER_DATATIME

#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)

Data timeout period.

◆ SDIO_FIFO_FIFODATA

#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)

Receive and transmit FIFO data

◆ SDIO_FIFOCNT_FIFOCOUNT

#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)

Remaining number of words to be written to or read from the FIFO

◆ SDIO_ICR_CCRCFAILC

#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)

CCRCFAIL flag clear bit

◆ SDIO_ICR_CEATAENDC

#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)

CEATAEND flag clear bit

◆ SDIO_ICR_CMDRENDC

#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)

CMDREND flag clear bit

◆ SDIO_ICR_CMDSENTC

#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)

CMDSENT flag clear bit

◆ SDIO_ICR_CTIMEOUTC

#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)

CTIMEOUT flag clear bit

◆ SDIO_ICR_DATAENDC

#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)

DATAEND flag clear bit

◆ SDIO_ICR_DBCKENDC

#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)

DBCKEND flag clear bit

◆ SDIO_ICR_DCRCFAILC

#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)

DCRCFAIL flag clear bit

◆ SDIO_ICR_DTIMEOUTC

#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)

DTIMEOUT flag clear bit

◆ SDIO_ICR_RXOVERRC

#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)

RXOVERR flag clear bit

◆ SDIO_ICR_SDIOITC

#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)

SDIOIT flag clear bit

◆ SDIO_ICR_STBITERRC

#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)

STBITERR flag clear bit

◆ SDIO_ICR_TXUNDERRC

#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)

TXUNDERR flag clear bit

◆ SDIO_MASK_CCRCFAILIE

#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)

Command CRC Fail Interrupt Enable

◆ SDIO_MASK_CEATAENDIE

#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)

CE-ATA command completion signal received Interrupt Enable

◆ SDIO_MASK_CMDACTIE

#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)

CCommand Acting Interrupt Enable

◆ SDIO_MASK_CMDRENDIE

#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)

Command Response Received Interrupt Enable

◆ SDIO_MASK_CMDSENTIE

#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)

Command Sent Interrupt Enable

◆ SDIO_MASK_CTIMEOUTIE

#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)

Command TimeOut Interrupt Enable

◆ SDIO_MASK_DATAENDIE

#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)

Data End Interrupt Enable

◆ SDIO_MASK_DBCKENDIE

#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)

Data Block End Interrupt Enable

◆ SDIO_MASK_DCRCFAILIE

#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)

Data CRC Fail Interrupt Enable

◆ SDIO_MASK_DTIMEOUTIE

#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)

Data TimeOut Interrupt Enable

◆ SDIO_MASK_RXACTIE

#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)

Data receive acting interrupt enabled

◆ SDIO_MASK_RXDAVLIE

#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)

Data available in Rx FIFO interrupt Enable

◆ SDIO_MASK_RXFIFOEIE

#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)

Rx FIFO Empty interrupt Enable

◆ SDIO_MASK_RXFIFOFIE

#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)

Rx FIFO Full interrupt Enable

◆ SDIO_MASK_RXFIFOHFIE

#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)

Rx FIFO Half Full interrupt Enable

◆ SDIO_MASK_RXOVERRIE

#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)

Rx FIFO OverRun Error Interrupt Enable

◆ SDIO_MASK_SDIOITIE

#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)

SDIO Mode Interrupt Received interrupt Enable

◆ SDIO_MASK_STBITERRIE

#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)

Start Bit Error Interrupt Enable

◆ SDIO_MASK_TXACTIE

#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)

Data Transmit Acting Interrupt Enable

◆ SDIO_MASK_TXDAVLIE

#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)

Data available in Tx FIFO interrupt Enable

◆ SDIO_MASK_TXFIFOEIE

#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)

Tx FIFO Empty interrupt Enable

◆ SDIO_MASK_TXFIFOFIE

#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)

Tx FIFO Full interrupt Enable

◆ SDIO_MASK_TXFIFOHEIE

#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)

Tx FIFO Half Empty interrupt Enable

◆ SDIO_MASK_TXUNDERRIE

#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)

Tx FIFO UnderRun Error Interrupt Enable

◆ SDIO_POWER_PWRCTRL

#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)

PWRCTRL[1:0] bits (Power supply control bits)

◆ SDIO_POWER_PWRCTRL_0

#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)

Bit 0

◆ SDIO_POWER_PWRCTRL_1

#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)

Bit 1

◆ SDIO_RESP0_CARDSTATUS0

#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)

Card Status

◆ SDIO_RESP1_CARDSTATUS1

#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)

Card Status

◆ SDIO_RESP2_CARDSTATUS2

#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)

Card Status

◆ SDIO_RESP3_CARDSTATUS3

#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)

Card Status

◆ SDIO_RESP4_CARDSTATUS4

#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)

Card Status

◆ SDIO_RESPCMD_RESPCMD

#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)

Response command index

◆ SDIO_STA_CCRCFAIL

#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)

Command response received (CRC check failed)

◆ SDIO_STA_CEATAEND

#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)

CE-ATA command completion signal received for CMD61

◆ SDIO_STA_CMDACT

#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)

Command transfer in progress

◆ SDIO_STA_CMDREND

#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)

Command response received (CRC check passed)

◆ SDIO_STA_CMDSENT

#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)

Command sent (no response required)

◆ SDIO_STA_CTIMEOUT

#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)

Command response timeout

◆ SDIO_STA_DATAEND

#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)

Data end (data counter, SDIDCOUNT, is zero)

◆ SDIO_STA_DBCKEND

#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)

Data block sent/received (CRC check passed)

◆ SDIO_STA_DCRCFAIL

#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)

Data block sent/received (CRC check failed)

◆ SDIO_STA_DTIMEOUT

#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)

Data timeout

◆ SDIO_STA_RXACT

#define SDIO_STA_RXACT   ((uint32_t)0x00002000)

Data receive in progress

◆ SDIO_STA_RXDAVL

#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)

Data available in receive FIFO

◆ SDIO_STA_RXFIFOE

#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)

Receive FIFO empty

◆ SDIO_STA_RXFIFOF

#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)

Receive FIFO full

◆ SDIO_STA_RXFIFOHF

#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)

Receive FIFO Half Full: there are at least 8 words in the FIFO

◆ SDIO_STA_RXOVERR

#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)

Received FIFO overrun error

◆ SDIO_STA_SDIOIT

#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)

SDIO interrupt received

◆ SDIO_STA_STBITERR

#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)

Start bit not detected on all data signals in wide bus mode

◆ SDIO_STA_TXACT

#define SDIO_STA_TXACT   ((uint32_t)0x00001000)

Data transmit in progress

◆ SDIO_STA_TXDAVL

#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)

Data available in transmit FIFO

◆ SDIO_STA_TXFIFOE

#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)

Transmit FIFO empty

◆ SDIO_STA_TXFIFOF

#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)

Transmit FIFO full

◆ SDIO_STA_TXFIFOHE

#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

◆ SDIO_STA_TXUNDERR

#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)

Transmit FIFO underrun error

◆ SPI_CR1_BIDIMODE

#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)

Bidirectional data mode enable

◆ SPI_CR1_BIDIOE

#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)

Output enable in bidirectional mode

◆ SPI_CR1_BR

#define SPI_CR1_BR   ((uint16_t)0x0038)

BR[2:0] bits (Baud Rate Control)

◆ SPI_CR1_BR_0

#define SPI_CR1_BR_0   ((uint16_t)0x0008)

Bit 0

◆ SPI_CR1_BR_1

#define SPI_CR1_BR_1   ((uint16_t)0x0010)

Bit 1

◆ SPI_CR1_BR_2

#define SPI_CR1_BR_2   ((uint16_t)0x0020)

Bit 2

◆ SPI_CR1_CPHA

#define SPI_CR1_CPHA   ((uint16_t)0x0001)

Clock Phase

◆ SPI_CR1_CPOL

#define SPI_CR1_CPOL   ((uint16_t)0x0002)

Clock Polarity

◆ SPI_CR1_CRCEN

#define SPI_CR1_CRCEN   ((uint16_t)0x2000)

Hardware CRC calculation enable

◆ SPI_CR1_CRCNEXT

#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)

Transmit CRC next

◆ SPI_CR1_DFF

#define SPI_CR1_DFF   ((uint16_t)0x0800)

Data Frame Format

◆ SPI_CR1_LSBFIRST

#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)

Frame Format

◆ SPI_CR1_MSTR

#define SPI_CR1_MSTR   ((uint16_t)0x0004)

Master Selection

◆ SPI_CR1_RXONLY

#define SPI_CR1_RXONLY   ((uint16_t)0x0400)

Receive only

◆ SPI_CR1_SPE

#define SPI_CR1_SPE   ((uint16_t)0x0040)

SPI Enable

◆ SPI_CR1_SSI

#define SPI_CR1_SSI   ((uint16_t)0x0100)

Internal slave select

◆ SPI_CR1_SSM

#define SPI_CR1_SSM   ((uint16_t)0x0200)

Software slave management

◆ SPI_CR2_ERRIE

#define SPI_CR2_ERRIE   ((uint8_t)0x20)

Error Interrupt Enable

◆ SPI_CR2_RXDMAEN

#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)

Rx Buffer DMA Enable

◆ SPI_CR2_RXNEIE

#define SPI_CR2_RXNEIE   ((uint8_t)0x40)

RX buffer Not Empty Interrupt Enable

◆ SPI_CR2_SSOE

#define SPI_CR2_SSOE   ((uint8_t)0x04)

SS Output Enable

◆ SPI_CR2_TXDMAEN

#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)

Tx Buffer DMA Enable

◆ SPI_CR2_TXEIE

#define SPI_CR2_TXEIE   ((uint8_t)0x80)

Tx buffer Empty Interrupt Enable

◆ SPI_CRCPR_CRCPOLY

#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)

CRC polynomial register

◆ SPI_DR_DR

#define SPI_DR_DR   ((uint16_t)0xFFFF)

Data Register

◆ SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)

Channel length (number of bits per audio channel)

◆ SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)

steady state clock polarity

◆ SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)

DATLEN[1:0] bits (Data length to be transferred)

◆ SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)

Bit 0

◆ SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)

Bit 1

◆ SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)

I2SCFG[1:0] bits (I2S configuration mode)

◆ SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)

Bit 0

◆ SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)

Bit 1

◆ SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)

I2S Enable

◆ SPI_I2SCFGR_I2SMOD

#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)

I2S mode selection

◆ SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)

I2SSTD[1:0] bits (I2S standard selection)

◆ SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)

Bit 0

◆ SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)

Bit 1

◆ SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)

PCM frame synchronization

◆ SPI_I2SPR_I2SDIV

#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)

I2S Linear prescaler

◆ SPI_I2SPR_MCKOE

#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)

Master Clock Output Enable

◆ SPI_I2SPR_ODD

#define SPI_I2SPR_ODD   ((uint16_t)0x0100)

Odd factor for the prescaler

◆ SPI_RXCRCR_RXCRC

#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)

Rx CRC Register

◆ SPI_SR_BSY

#define SPI_SR_BSY   ((uint8_t)0x80)

Busy flag

◆ SPI_SR_CHSIDE

#define SPI_SR_CHSIDE   ((uint8_t)0x04)

Channel side

◆ SPI_SR_CRCERR

#define SPI_SR_CRCERR   ((uint8_t)0x10)

CRC Error flag

◆ SPI_SR_MODF

#define SPI_SR_MODF   ((uint8_t)0x20)

Mode fault

◆ SPI_SR_OVR

#define SPI_SR_OVR   ((uint8_t)0x40)

Overrun flag

◆ SPI_SR_RXNE

#define SPI_SR_RXNE   ((uint8_t)0x01)

Receive buffer Not Empty

◆ SPI_SR_TXE

#define SPI_SR_TXE   ((uint8_t)0x02)

Transmit buffer Empty

◆ SPI_SR_UDR

#define SPI_SR_UDR   ((uint8_t)0x08)

Underrun flag

◆ SPI_TXCRCR_TXCRC

#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)

Tx CRC Register

◆ SYSCFG_CMPCR_CMP_PD

#define SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)

Compensation cell ready flag

◆ SYSCFG_CMPCR_READY

#define SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)

Compensation cell power-down

◆ SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)

EXTI 0 configuration

◆ SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)

EXTI0 configuration

PA[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)

PB[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)

PC[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)

PD[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)

PE[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)

PF[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PG

#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)

PG[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PH

#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)

PH[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PI

#define SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)

PI[0] pin

◆ SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)

EXTI 1 configuration

◆ SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)

EXTI1 configuration

PA[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)

PB[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)

PC[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)

PD[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)

PE[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)

PF[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PG

#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)

PG[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PH

#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)

PH[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PI

#define SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)

PI[1] pin

◆ SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)

EXTI 2 configuration

◆ SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)

EXTI2 configuration

PA[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)

PB[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)

PC[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)

PD[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)

PE[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)

PF[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PG

#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)

PG[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PH

#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)

PH[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PI

#define SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)

PI[2] pin

◆ SYSCFG_EXTICR1_EXTI3

#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)

EXTI 3 configuration

◆ SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)

EXTI3 configuration

PA[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)

PB[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)

PC[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)

PD[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)

PE[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)

PF[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)

PG[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PH

#define SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)

PH[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PI

#define SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)

PI[3] pin

◆ SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)

EXTI 4 configuration

◆ SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)

EXTI4 configuration

PA[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)

PB[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)

PC[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)

PD[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)

PE[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)

PF[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PG

#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)

PG[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PH

#define SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)

PH[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PI

#define SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)

PI[4] pin

◆ SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)

EXTI 5 configuration

◆ SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)

EXTI5 configuration

PA[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)

PB[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)

PC[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)

PD[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)

PE[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)

PF[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PG

#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)

PG[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PH

#define SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)

PH[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PI

#define SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)

PI[5] pin

◆ SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)

EXTI 6 configuration

◆ SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)

EXTI6 configuration

PA[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)

PB[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)

PC[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)

PD[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)

PE[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)

PF[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PG

#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)

PG[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PH

#define SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)

PH[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PI

#define SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)

PI[6] pin

◆ SYSCFG_EXTICR2_EXTI7

#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)

EXTI 7 configuration

◆ SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)

EXTI7 configuration

PA[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)

PB[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)

PC[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)

PD[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)

PE[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)

PF[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)

PG[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PH

#define SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)

PH[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PI

#define SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)

PI[7] pin

◆ SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)

EXTI 10 configuration

◆ SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)

EXTI10 configuration

PA[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)

PB[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)

PC[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)

PD[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)

PE[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)

PF[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PG

#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)

PG[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PH

#define SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)

PH[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PI

#define SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)

PI[10] pin

◆ SYSCFG_EXTICR3_EXTI11

#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)

EXTI 11 configuration

◆ SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)

EXTI11 configuration

PA[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)

PB[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)

PC[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)

PD[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)

PE[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)

PF[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PG

#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)

PG[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PH

#define SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)

PH[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PI

#define SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)

PI[11] pin

◆ SYSCFG_EXTICR3_EXTI12_PH

#define SYSCFG_EXTICR3_EXTI12_PH   ((uint16_t)0x0007)

PH[12] pin

◆ SYSCFG_EXTICR3_EXTI13_PH

#define SYSCFG_EXTICR3_EXTI13_PH   ((uint16_t)0x0070)

PH[13] pin

◆ SYSCFG_EXTICR3_EXTI14_PH

#define SYSCFG_EXTICR3_EXTI14_PH   ((uint16_t)0x0700)

PH[14] pin

◆ SYSCFG_EXTICR3_EXTI15_PH

#define SYSCFG_EXTICR3_EXTI15_PH   ((uint16_t)0x7000)

PH[15] pin

◆ SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)

EXTI 8 configuration

◆ SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)

EXTI8 configuration

PA[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)

PB[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)

PC[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)

PD[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)

PE[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)

PF[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PG

#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)

PG[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PH

#define SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)

PH[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PI

#define SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)

PI[8] pin

◆ SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)

EXTI 9 configuration

◆ SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)

EXTI9 configuration

PA[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)

PB[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)

PC[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)

PD[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)

PE[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)

PF[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PG

#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)

PG[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PH

#define SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)

PH[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PI

#define SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)

PI[9] pin

◆ SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)

EXTI 12 configuration

◆ SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)

EXTI12 configuration

PA[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)

PB[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)

PC[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)

PD[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)

PE[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)

PF[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PG

#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)

PG[12] pin

◆ SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)

EXTI 13 configuration

◆ SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)

EXTI13 configuration

PA[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)

PB[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)

PC[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)

PD[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)

PE[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)

PF[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PG

#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)

PG[13] pin

◆ SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)

EXTI 14 configuration

◆ SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)

EXTI14 configuration

PA[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)

PB[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)

PC[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)

PD[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)

PE[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)

PF[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PG

#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)

PG[14] pin

◆ SYSCFG_EXTICR4_EXTI15

#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)

EXTI 15 configuration

◆ SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)

EXTI15 configuration

PA[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)

PB[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)

PC[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)

PD[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)

PE[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)

PF[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PG

#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)

PG[15] pin

◆ SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)

SYSCFG_Memory Remap Config

◆ SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)

◆ SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)

◆ SYSCFG_PMC_MII_RMII

#define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL

◆ SYSCFG_PMC_MII_RMII_SEL

#define SYSCFG_PMC_MII_RMII_SEL   ((uint32_t)0x00800000)

Ethernet PHY interface selection

◆ TIM_ARR_ARR

#define TIM_ARR_ARR   ((uint16_t)0xFFFF)

actual auto-reload Value

◆ TIM_BDTR_AOE

#define TIM_BDTR_AOE   ((uint16_t)0x4000)

Automatic Output enable

◆ TIM_BDTR_BKE

#define TIM_BDTR_BKE   ((uint16_t)0x1000)

Break enable

◆ TIM_BDTR_BKP

#define TIM_BDTR_BKP   ((uint16_t)0x2000)

Break Polarity

◆ TIM_BDTR_DTG

#define TIM_BDTR_DTG   ((uint16_t)0x00FF)

DTG[0:7] bits (Dead-Time Generator set-up)

◆ TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)

Bit 0

◆ TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)

Bit 1

◆ TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)

Bit 2

◆ TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)

Bit 3

◆ TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)

Bit 4

◆ TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)

Bit 5

◆ TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)

Bit 6

◆ TIM_BDTR_DTG_7

#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)

Bit 7

◆ TIM_BDTR_LOCK

#define TIM_BDTR_LOCK   ((uint16_t)0x0300)

LOCK[1:0] bits (Lock Configuration)

◆ TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)

Bit 0

◆ TIM_BDTR_LOCK_1

#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)

Bit 1

◆ TIM_BDTR_MOE

#define TIM_BDTR_MOE   ((uint16_t)0x8000)

Main Output enable

◆ TIM_BDTR_OSSI

#define TIM_BDTR_OSSI   ((uint16_t)0x0400)

Off-State Selection for Idle mode

◆ TIM_BDTR_OSSR

#define TIM_BDTR_OSSR   ((uint16_t)0x0800)

Off-State Selection for Run mode

◆ TIM_CCER_CC1E

#define TIM_CCER_CC1E   ((uint16_t)0x0001)

Capture/Compare 1 output enable

◆ TIM_CCER_CC1NE

#define TIM_CCER_CC1NE   ((uint16_t)0x0004)

Capture/Compare 1 Complementary output enable

◆ TIM_CCER_CC1NP

#define TIM_CCER_CC1NP   ((uint16_t)0x0008)

Capture/Compare 1 Complementary output Polarity

◆ TIM_CCER_CC1P

#define TIM_CCER_CC1P   ((uint16_t)0x0002)

Capture/Compare 1 output Polarity

◆ TIM_CCER_CC2E

#define TIM_CCER_CC2E   ((uint16_t)0x0010)

Capture/Compare 2 output enable

◆ TIM_CCER_CC2NE

#define TIM_CCER_CC2NE   ((uint16_t)0x0040)

Capture/Compare 2 Complementary output enable

◆ TIM_CCER_CC2NP

#define TIM_CCER_CC2NP   ((uint16_t)0x0080)

Capture/Compare 2 Complementary output Polarity

◆ TIM_CCER_CC2P

#define TIM_CCER_CC2P   ((uint16_t)0x0020)

Capture/Compare 2 output Polarity

◆ TIM_CCER_CC3E

#define TIM_CCER_CC3E   ((uint16_t)0x0100)

Capture/Compare 3 output enable

◆ TIM_CCER_CC3NE

#define TIM_CCER_CC3NE   ((uint16_t)0x0400)

Capture/Compare 3 Complementary output enable

◆ TIM_CCER_CC3NP

#define TIM_CCER_CC3NP   ((uint16_t)0x0800)

Capture/Compare 3 Complementary output Polarity

◆ TIM_CCER_CC3P

#define TIM_CCER_CC3P   ((uint16_t)0x0200)

Capture/Compare 3 output Polarity

◆ TIM_CCER_CC4E

#define TIM_CCER_CC4E   ((uint16_t)0x1000)

Capture/Compare 4 output enable

◆ TIM_CCER_CC4NP

#define TIM_CCER_CC4NP   ((uint16_t)0x8000)

Capture/Compare 4 Complementary output Polarity

◆ TIM_CCER_CC4P

#define TIM_CCER_CC4P   ((uint16_t)0x2000)

Capture/Compare 4 output Polarity

◆ TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)

CC1S[1:0] bits (Capture/Compare 1 Selection)

◆ TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)

Bit 0

◆ TIM_CCMR1_CC1S_1

#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)

Bit 1

◆ TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)

CC2S[1:0] bits (Capture/Compare 2 Selection)

◆ TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)

Bit 0

◆ TIM_CCMR1_CC2S_1

#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)

Bit 1

◆ TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)

IC1F[3:0] bits (Input Capture 1 Filter)

◆ TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)

Bit 0

◆ TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)

Bit 1

◆ TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)

Bit 2

◆ TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)

Bit 3

◆ TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

◆ TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)

Bit 0

◆ TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)

Bit 1

◆ TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)

IC2F[3:0] bits (Input Capture 2 Filter)

◆ TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)

Bit 0

◆ TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)

Bit 1

◆ TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)

Bit 2

◆ TIM_CCMR1_IC2F_3

#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)

Bit 3

◆ TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

◆ TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)

Bit 0

◆ TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)

Bit 1

◆ TIM_CCMR1_OC1CE

#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)

Output Compare 1Clear Enable

◆ TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)

Output Compare 1 Fast enable

◆ TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)

OC1M[2:0] bits (Output Compare 1 Mode)

◆ TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)

Bit 0

◆ TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)

Bit 1

◆ TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)

Bit 2

◆ TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)

Output Compare 1 Preload enable

◆ TIM_CCMR1_OC2CE

#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)

Output Compare 2 Clear Enable

◆ TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)

Output Compare 2 Fast enable

◆ TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)

OC2M[2:0] bits (Output Compare 2 Mode)

◆ TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)

Bit 0

◆ TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)

Bit 1

◆ TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)

Bit 2

◆ TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)

Output Compare 2 Preload enable

◆ TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)

CC3S[1:0] bits (Capture/Compare 3 Selection)

◆ TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)

Bit 0

◆ TIM_CCMR2_CC3S_1

#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)

Bit 1

◆ TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)

CC4S[1:0] bits (Capture/Compare 4 Selection)

◆ TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)

Bit 0

◆ TIM_CCMR2_CC4S_1

#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)

Bit 1

◆ TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)

IC3F[3:0] bits (Input Capture 3 Filter)

◆ TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)

Bit 0

◆ TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)

Bit 1

◆ TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)

Bit 2

◆ TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)

Bit 3

◆ TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

◆ TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)

Bit 0

◆ TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)

Bit 1

◆ TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)

IC4F[3:0] bits (Input Capture 4 Filter)

◆ TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)

Bit 0

◆ TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)

Bit 1

◆ TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)

Bit 2

◆ TIM_CCMR2_IC4F_3

#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)

Bit 3

◆ TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

◆ TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)

Bit 0

◆ TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)

Bit 1

◆ TIM_CCMR2_OC3CE

#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)

Output Compare 3 Clear Enable

◆ TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)

Output Compare 3 Fast enable

◆ TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)

OC3M[2:0] bits (Output Compare 3 Mode)

◆ TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)

Bit 0

◆ TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)

Bit 1

◆ TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)

Bit 2

◆ TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)

Output Compare 3 Preload enable

◆ TIM_CCMR2_OC4CE

#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)

Output Compare 4 Clear Enable

◆ TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)

Output Compare 4 Fast enable

◆ TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)

OC4M[2:0] bits (Output Compare 4 Mode)

◆ TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)

Bit 0

◆ TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)

Bit 1

◆ TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)

Bit 2

◆ TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)

Output Compare 4 Preload enable

◆ TIM_CCR1_CCR1

#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)

Capture/Compare 1 Value

◆ TIM_CCR2_CCR2

#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)

Capture/Compare 2 Value

◆ TIM_CCR3_CCR3

#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)

Capture/Compare 3 Value

◆ TIM_CCR4_CCR4

#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)

Capture/Compare 4 Value

◆ TIM_CNT_CNT

#define TIM_CNT_CNT   ((uint16_t)0xFFFF)

Counter Value

◆ TIM_CR1_ARPE

#define TIM_CR1_ARPE   ((uint16_t)0x0080)

Auto-reload preload enable

◆ TIM_CR1_CEN

#define TIM_CR1_CEN   ((uint16_t)0x0001)

Counter enable

◆ TIM_CR1_CKD

#define TIM_CR1_CKD   ((uint16_t)0x0300)

CKD[1:0] bits (clock division)

◆ TIM_CR1_CKD_0

#define TIM_CR1_CKD_0   ((uint16_t)0x0100)

Bit 0

◆ TIM_CR1_CKD_1

#define TIM_CR1_CKD_1   ((uint16_t)0x0200)

Bit 1

◆ TIM_CR1_CMS

#define TIM_CR1_CMS   ((uint16_t)0x0060)

CMS[1:0] bits (Center-aligned mode selection)

◆ TIM_CR1_CMS_0

#define TIM_CR1_CMS_0   ((uint16_t)0x0020)

Bit 0

◆ TIM_CR1_CMS_1

#define TIM_CR1_CMS_1   ((uint16_t)0x0040)

Bit 1

◆ TIM_CR1_DIR

#define TIM_CR1_DIR   ((uint16_t)0x0010)

Direction

◆ TIM_CR1_OPM

#define TIM_CR1_OPM   ((uint16_t)0x0008)

One pulse mode

◆ TIM_CR1_UDIS

#define TIM_CR1_UDIS   ((uint16_t)0x0002)

Update disable

◆ TIM_CR1_URS

#define TIM_CR1_URS   ((uint16_t)0x0004)

Update request source

◆ TIM_CR2_CCDS

#define TIM_CR2_CCDS   ((uint16_t)0x0008)

Capture/Compare DMA Selection

◆ TIM_CR2_CCPC

#define TIM_CR2_CCPC   ((uint16_t)0x0001)

Capture/Compare Preloaded Control

◆ TIM_CR2_CCUS

#define TIM_CR2_CCUS   ((uint16_t)0x0004)

Capture/Compare Control Update Selection

◆ TIM_CR2_MMS

#define TIM_CR2_MMS   ((uint16_t)0x0070)

MMS[2:0] bits (Master Mode Selection)

◆ TIM_CR2_MMS_0

#define TIM_CR2_MMS_0   ((uint16_t)0x0010)

Bit 0

◆ TIM_CR2_MMS_1

#define TIM_CR2_MMS_1   ((uint16_t)0x0020)

Bit 1

◆ TIM_CR2_MMS_2

#define TIM_CR2_MMS_2   ((uint16_t)0x0040)

Bit 2

◆ TIM_CR2_OIS1

#define TIM_CR2_OIS1   ((uint16_t)0x0100)

Output Idle state 1 (OC1 output)

◆ TIM_CR2_OIS1N

#define TIM_CR2_OIS1N   ((uint16_t)0x0200)

Output Idle state 1 (OC1N output)

◆ TIM_CR2_OIS2

#define TIM_CR2_OIS2   ((uint16_t)0x0400)

Output Idle state 2 (OC2 output)

◆ TIM_CR2_OIS2N

#define TIM_CR2_OIS2N   ((uint16_t)0x0800)

Output Idle state 2 (OC2N output)

◆ TIM_CR2_OIS3

#define TIM_CR2_OIS3   ((uint16_t)0x1000)

Output Idle state 3 (OC3 output)

◆ TIM_CR2_OIS3N

#define TIM_CR2_OIS3N   ((uint16_t)0x2000)

Output Idle state 3 (OC3N output)

◆ TIM_CR2_OIS4

#define TIM_CR2_OIS4   ((uint16_t)0x4000)

Output Idle state 4 (OC4 output)

◆ TIM_CR2_TI1S

#define TIM_CR2_TI1S   ((uint16_t)0x0080)

TI1 Selection

◆ TIM_DCR_DBA

#define TIM_DCR_DBA   ((uint16_t)0x001F)

DBA[4:0] bits (DMA Base Address)

◆ TIM_DCR_DBA_0

#define TIM_DCR_DBA_0   ((uint16_t)0x0001)

Bit 0

◆ TIM_DCR_DBA_1

#define TIM_DCR_DBA_1   ((uint16_t)0x0002)

Bit 1

◆ TIM_DCR_DBA_2

#define TIM_DCR_DBA_2   ((uint16_t)0x0004)

Bit 2

◆ TIM_DCR_DBA_3

#define TIM_DCR_DBA_3   ((uint16_t)0x0008)

Bit 3

◆ TIM_DCR_DBA_4

#define TIM_DCR_DBA_4   ((uint16_t)0x0010)

Bit 4

◆ TIM_DCR_DBL

#define TIM_DCR_DBL   ((uint16_t)0x1F00)

DBL[4:0] bits (DMA Burst Length)

◆ TIM_DCR_DBL_0

#define TIM_DCR_DBL_0   ((uint16_t)0x0100)

Bit 0

◆ TIM_DCR_DBL_1

#define TIM_DCR_DBL_1   ((uint16_t)0x0200)

Bit 1

◆ TIM_DCR_DBL_2

#define TIM_DCR_DBL_2   ((uint16_t)0x0400)

Bit 2

◆ TIM_DCR_DBL_3

#define TIM_DCR_DBL_3   ((uint16_t)0x0800)

Bit 3

◆ TIM_DCR_DBL_4

#define TIM_DCR_DBL_4   ((uint16_t)0x1000)

Bit 4

◆ TIM_DIER_BIE

#define TIM_DIER_BIE   ((uint16_t)0x0080)

Break interrupt enable

◆ TIM_DIER_CC1DE

#define TIM_DIER_CC1DE   ((uint16_t)0x0200)

Capture/Compare 1 DMA request enable

◆ TIM_DIER_CC1IE

#define TIM_DIER_CC1IE   ((uint16_t)0x0002)

Capture/Compare 1 interrupt enable

◆ TIM_DIER_CC2DE

#define TIM_DIER_CC2DE   ((uint16_t)0x0400)

Capture/Compare 2 DMA request enable

◆ TIM_DIER_CC2IE

#define TIM_DIER_CC2IE   ((uint16_t)0x0004)

Capture/Compare 2 interrupt enable

◆ TIM_DIER_CC3DE

#define TIM_DIER_CC3DE   ((uint16_t)0x0800)

Capture/Compare 3 DMA request enable

◆ TIM_DIER_CC3IE

#define TIM_DIER_CC3IE   ((uint16_t)0x0008)

Capture/Compare 3 interrupt enable

◆ TIM_DIER_CC4DE

#define TIM_DIER_CC4DE   ((uint16_t)0x1000)

Capture/Compare 4 DMA request enable

◆ TIM_DIER_CC4IE

#define TIM_DIER_CC4IE   ((uint16_t)0x0010)

Capture/Compare 4 interrupt enable

◆ TIM_DIER_COMDE

#define TIM_DIER_COMDE   ((uint16_t)0x2000)

COM DMA request enable

◆ TIM_DIER_COMIE

#define TIM_DIER_COMIE   ((uint16_t)0x0020)

COM interrupt enable

◆ TIM_DIER_TDE

#define TIM_DIER_TDE   ((uint16_t)0x4000)

Trigger DMA request enable

◆ TIM_DIER_TIE

#define TIM_DIER_TIE   ((uint16_t)0x0040)

Trigger interrupt enable

◆ TIM_DIER_UDE

#define TIM_DIER_UDE   ((uint16_t)0x0100)

Update DMA request enable

◆ TIM_DIER_UIE

#define TIM_DIER_UIE   ((uint16_t)0x0001)

Update interrupt enable

◆ TIM_DMAR_DMAB

#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)

DMA register for burst accesses

◆ TIM_EGR_BG

#define TIM_EGR_BG   ((uint8_t)0x80)

Break Generation

◆ TIM_EGR_CC1G

#define TIM_EGR_CC1G   ((uint8_t)0x02)

Capture/Compare 1 Generation

◆ TIM_EGR_CC2G

#define TIM_EGR_CC2G   ((uint8_t)0x04)

Capture/Compare 2 Generation

◆ TIM_EGR_CC3G

#define TIM_EGR_CC3G   ((uint8_t)0x08)

Capture/Compare 3 Generation

◆ TIM_EGR_CC4G

#define TIM_EGR_CC4G   ((uint8_t)0x10)

Capture/Compare 4 Generation

◆ TIM_EGR_COMG

#define TIM_EGR_COMG   ((uint8_t)0x20)

Capture/Compare Control Update Generation

◆ TIM_EGR_TG

#define TIM_EGR_TG   ((uint8_t)0x40)

Trigger Generation

◆ TIM_EGR_UG

#define TIM_EGR_UG   ((uint8_t)0x01)

Update Generation

◆ TIM_OR_ITR1_RMP

#define TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)

ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

◆ TIM_OR_ITR1_RMP_0

#define TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)

Bit 0

◆ TIM_OR_ITR1_RMP_1

#define TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)

Bit 1

◆ TIM_OR_TI4_RMP

#define TIM_OR_TI4_RMP   ((uint16_t)0x00C0)

TI4_RMP[1:0] bits (TIM5 Input 4 remap)

◆ TIM_OR_TI4_RMP_0

#define TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)

Bit 0

◆ TIM_OR_TI4_RMP_1

#define TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)

Bit 1

◆ TIM_PSC_PSC

#define TIM_PSC_PSC   ((uint16_t)0xFFFF)

Prescaler Value

◆ TIM_RCR_REP

#define TIM_RCR_REP   ((uint8_t)0xFF)

Repetition Counter Value

◆ TIM_SMCR_ECE

#define TIM_SMCR_ECE   ((uint16_t)0x4000)

External clock enable

◆ TIM_SMCR_ETF

#define TIM_SMCR_ETF   ((uint16_t)0x0F00)

ETF[3:0] bits (External trigger filter)

◆ TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)

Bit 0

◆ TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)

Bit 1

◆ TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)

Bit 2

◆ TIM_SMCR_ETF_3

#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)

Bit 3

◆ TIM_SMCR_ETP

#define TIM_SMCR_ETP   ((uint16_t)0x8000)

External trigger polarity

◆ TIM_SMCR_ETPS

#define TIM_SMCR_ETPS   ((uint16_t)0x3000)

ETPS[1:0] bits (External trigger prescaler)

◆ TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)

Bit 0

◆ TIM_SMCR_ETPS_1

#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)

Bit 1

◆ TIM_SMCR_MSM

#define TIM_SMCR_MSM   ((uint16_t)0x0080)

Master/slave mode

◆ TIM_SMCR_SMS

#define TIM_SMCR_SMS   ((uint16_t)0x0007)

SMS[2:0] bits (Slave mode selection)

◆ TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)

Bit 0

◆ TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)

Bit 1

◆ TIM_SMCR_SMS_2

#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)

Bit 2

◆ TIM_SMCR_TS

#define TIM_SMCR_TS   ((uint16_t)0x0070)

TS[2:0] bits (Trigger selection)

◆ TIM_SMCR_TS_0

#define TIM_SMCR_TS_0   ((uint16_t)0x0010)

Bit 0

◆ TIM_SMCR_TS_1

#define TIM_SMCR_TS_1   ((uint16_t)0x0020)

Bit 1

◆ TIM_SMCR_TS_2

#define TIM_SMCR_TS_2   ((uint16_t)0x0040)

Bit 2

◆ TIM_SR_BIF

#define TIM_SR_BIF   ((uint16_t)0x0080)

Break interrupt Flag

◆ TIM_SR_CC1IF

#define TIM_SR_CC1IF   ((uint16_t)0x0002)

Capture/Compare 1 interrupt Flag

◆ TIM_SR_CC1OF

#define TIM_SR_CC1OF   ((uint16_t)0x0200)

Capture/Compare 1 Overcapture Flag

◆ TIM_SR_CC2IF

#define TIM_SR_CC2IF   ((uint16_t)0x0004)

Capture/Compare 2 interrupt Flag

◆ TIM_SR_CC2OF

#define TIM_SR_CC2OF   ((uint16_t)0x0400)

Capture/Compare 2 Overcapture Flag

◆ TIM_SR_CC3IF

#define TIM_SR_CC3IF   ((uint16_t)0x0008)

Capture/Compare 3 interrupt Flag

◆ TIM_SR_CC3OF

#define TIM_SR_CC3OF   ((uint16_t)0x0800)

Capture/Compare 3 Overcapture Flag

◆ TIM_SR_CC4IF

#define TIM_SR_CC4IF   ((uint16_t)0x0010)

Capture/Compare 4 interrupt Flag

◆ TIM_SR_CC4OF

#define TIM_SR_CC4OF   ((uint16_t)0x1000)

Capture/Compare 4 Overcapture Flag

◆ TIM_SR_COMIF

#define TIM_SR_COMIF   ((uint16_t)0x0020)

COM interrupt Flag

◆ TIM_SR_TIF

#define TIM_SR_TIF   ((uint16_t)0x0040)

Trigger interrupt Flag

◆ TIM_SR_UIF

#define TIM_SR_UIF   ((uint16_t)0x0001)

Update interrupt Flag

◆ USART_BRR_DIV_Fraction

#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)

Fraction of USARTDIV

◆ USART_BRR_DIV_Mantissa

#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)

Mantissa of USARTDIV

◆ USART_CR1_IDLEIE

#define USART_CR1_IDLEIE   ((uint16_t)0x0010)

IDLE Interrupt Enable

◆ USART_CR1_M

#define USART_CR1_M   ((uint16_t)0x1000)

Word length

◆ USART_CR1_OVER8

#define USART_CR1_OVER8   ((uint16_t)0x8000)

USART Oversampling by 8 enable

◆ USART_CR1_PCE

#define USART_CR1_PCE   ((uint16_t)0x0400)

Parity Control Enable

◆ USART_CR1_PEIE

#define USART_CR1_PEIE   ((uint16_t)0x0100)

PE Interrupt Enable

◆ USART_CR1_PS

#define USART_CR1_PS   ((uint16_t)0x0200)

Parity Selection

◆ USART_CR1_RE

#define USART_CR1_RE   ((uint16_t)0x0004)

Receiver Enable

◆ USART_CR1_RWU

#define USART_CR1_RWU   ((uint16_t)0x0002)

Receiver wakeup

◆ USART_CR1_RXNEIE

#define USART_CR1_RXNEIE   ((uint16_t)0x0020)

RXNE Interrupt Enable

◆ USART_CR1_SBK

#define USART_CR1_SBK   ((uint16_t)0x0001)

Send Break

◆ USART_CR1_TCIE

#define USART_CR1_TCIE   ((uint16_t)0x0040)

Transmission Complete Interrupt Enable

◆ USART_CR1_TE

#define USART_CR1_TE   ((uint16_t)0x0008)

Transmitter Enable

◆ USART_CR1_TXEIE

#define USART_CR1_TXEIE   ((uint16_t)0x0080)

PE Interrupt Enable

◆ USART_CR1_UE

#define USART_CR1_UE   ((uint16_t)0x2000)

USART Enable

◆ USART_CR1_WAKE

#define USART_CR1_WAKE   ((uint16_t)0x0800)

Wakeup method

◆ USART_CR2_ADD

#define USART_CR2_ADD   ((uint16_t)0x000F)

Address of the USART node

◆ USART_CR2_CLKEN

#define USART_CR2_CLKEN   ((uint16_t)0x0800)

Clock Enable

◆ USART_CR2_CPHA

#define USART_CR2_CPHA   ((uint16_t)0x0200)

Clock Phase

◆ USART_CR2_CPOL

#define USART_CR2_CPOL   ((uint16_t)0x0400)

Clock Polarity

◆ USART_CR2_LBCL

#define USART_CR2_LBCL   ((uint16_t)0x0100)

Last Bit Clock pulse

◆ USART_CR2_LBDIE

#define USART_CR2_LBDIE   ((uint16_t)0x0040)

LIN Break Detection Interrupt Enable

◆ USART_CR2_LBDL

#define USART_CR2_LBDL   ((uint16_t)0x0020)

LIN Break Detection Length

◆ USART_CR2_LINEN

#define USART_CR2_LINEN   ((uint16_t)0x4000)

LIN mode enable

◆ USART_CR2_STOP

#define USART_CR2_STOP   ((uint16_t)0x3000)

STOP[1:0] bits (STOP bits)

◆ USART_CR2_STOP_0

#define USART_CR2_STOP_0   ((uint16_t)0x1000)

Bit 0

◆ USART_CR2_STOP_1

#define USART_CR2_STOP_1   ((uint16_t)0x2000)

Bit 1

◆ USART_CR3_CTSE

#define USART_CR3_CTSE   ((uint16_t)0x0200)

CTS Enable

◆ USART_CR3_CTSIE

#define USART_CR3_CTSIE   ((uint16_t)0x0400)

CTS Interrupt Enable

◆ USART_CR3_DMAR

#define USART_CR3_DMAR   ((uint16_t)0x0040)

DMA Enable Receiver

◆ USART_CR3_DMAT

#define USART_CR3_DMAT   ((uint16_t)0x0080)

DMA Enable Transmitter

◆ USART_CR3_EIE

#define USART_CR3_EIE   ((uint16_t)0x0001)

Error Interrupt Enable

◆ USART_CR3_HDSEL

#define USART_CR3_HDSEL   ((uint16_t)0x0008)

Half-Duplex Selection

◆ USART_CR3_IREN

#define USART_CR3_IREN   ((uint16_t)0x0002)

IrDA mode Enable

◆ USART_CR3_IRLP

#define USART_CR3_IRLP   ((uint16_t)0x0004)

IrDA Low-Power

◆ USART_CR3_NACK

#define USART_CR3_NACK   ((uint16_t)0x0010)

Smartcard NACK enable

◆ USART_CR3_ONEBIT

#define USART_CR3_ONEBIT   ((uint16_t)0x0800)

USART One bit method enable

◆ USART_CR3_RTSE

#define USART_CR3_RTSE   ((uint16_t)0x0100)

RTS Enable

◆ USART_CR3_SCEN

#define USART_CR3_SCEN   ((uint16_t)0x0020)

Smartcard mode enable

◆ USART_DR_DR

#define USART_DR_DR   ((uint16_t)0x01FF)

Data value

◆ USART_GTPR_GT

#define USART_GTPR_GT   ((uint16_t)0xFF00)

Guard time value

◆ USART_GTPR_PSC

#define USART_GTPR_PSC   ((uint16_t)0x00FF)

PSC[7:0] bits (Prescaler value)

◆ USART_GTPR_PSC_0

#define USART_GTPR_PSC_0   ((uint16_t)0x0001)

Bit 0

◆ USART_GTPR_PSC_1

#define USART_GTPR_PSC_1   ((uint16_t)0x0002)

Bit 1

◆ USART_GTPR_PSC_2

#define USART_GTPR_PSC_2   ((uint16_t)0x0004)

Bit 2

◆ USART_GTPR_PSC_3

#define USART_GTPR_PSC_3   ((uint16_t)0x0008)

Bit 3

◆ USART_GTPR_PSC_4

#define USART_GTPR_PSC_4   ((uint16_t)0x0010)

Bit 4

◆ USART_GTPR_PSC_5

#define USART_GTPR_PSC_5   ((uint16_t)0x0020)

Bit 5

◆ USART_GTPR_PSC_6

#define USART_GTPR_PSC_6   ((uint16_t)0x0040)

Bit 6

◆ USART_GTPR_PSC_7

#define USART_GTPR_PSC_7   ((uint16_t)0x0080)

Bit 7

◆ USART_SR_CTS

#define USART_SR_CTS   ((uint16_t)0x0200)

CTS Flag

◆ USART_SR_FE

#define USART_SR_FE   ((uint16_t)0x0002)

Framing Error

◆ USART_SR_IDLE

#define USART_SR_IDLE   ((uint16_t)0x0010)

IDLE line detected

◆ USART_SR_LBD

#define USART_SR_LBD   ((uint16_t)0x0100)

LIN Break Detection Flag

◆ USART_SR_NE

#define USART_SR_NE   ((uint16_t)0x0004)

Noise Error Flag

◆ USART_SR_ORE

#define USART_SR_ORE   ((uint16_t)0x0008)

OverRun Error

◆ USART_SR_PE

#define USART_SR_PE   ((uint16_t)0x0001)

Parity Error

◆ USART_SR_RXNE

#define USART_SR_RXNE   ((uint16_t)0x0020)

Read Data Register Not Empty

◆ USART_SR_TC

#define USART_SR_TC   ((uint16_t)0x0040)

Transmission Complete

◆ USART_SR_TXE

#define USART_SR_TXE   ((uint16_t)0x0080)

Transmit Data Register Empty

◆ WWDG_CFR_EWI

#define WWDG_CFR_EWI   ((uint16_t)0x0200)

Early Wakeup Interrupt

◆ WWDG_CFR_W

#define WWDG_CFR_W   ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

◆ WWDG_CFR_W0

#define WWDG_CFR_W0   ((uint16_t)0x0001)

Bit 0

◆ WWDG_CFR_W1

#define WWDG_CFR_W1   ((uint16_t)0x0002)

Bit 1

◆ WWDG_CFR_W2

#define WWDG_CFR_W2   ((uint16_t)0x0004)

Bit 2

◆ WWDG_CFR_W3

#define WWDG_CFR_W3   ((uint16_t)0x0008)

Bit 3

◆ WWDG_CFR_W4

#define WWDG_CFR_W4   ((uint16_t)0x0010)

Bit 4

◆ WWDG_CFR_W5

#define WWDG_CFR_W5   ((uint16_t)0x0020)

Bit 5

◆ WWDG_CFR_W6

#define WWDG_CFR_W6   ((uint16_t)0x0040)

Bit 6

◆ WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

◆ WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)

Bit 0

◆ WWDG_CFR_WDGTB1

#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)

Bit 1

◆ WWDG_CR_T

#define WWDG_CR_T   ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

◆ WWDG_CR_T0

#define WWDG_CR_T0   ((uint8_t)0x01)

Bit 0

◆ WWDG_CR_T1

#define WWDG_CR_T1   ((uint8_t)0x02)

Bit 1

◆ WWDG_CR_T2

#define WWDG_CR_T2   ((uint8_t)0x04)

Bit 2

◆ WWDG_CR_T3

#define WWDG_CR_T3   ((uint8_t)0x08)

Bit 3

◆ WWDG_CR_T4

#define WWDG_CR_T4   ((uint8_t)0x10)

Bit 4

◆ WWDG_CR_T5

#define WWDG_CR_T5   ((uint8_t)0x20)

Bit 5

◆ WWDG_CR_T6

#define WWDG_CR_T6   ((uint8_t)0x40)

Bit 6

◆ WWDG_CR_WDGA

#define WWDG_CR_WDGA   ((uint8_t)0x80)

Activation bit

◆ WWDG_SR_EWIF

#define WWDG_SR_EWIF   ((uint8_t)0x01)

Early Wakeup Interrupt Flag